半導體 (Semiconductor)
複雜的圖案化方案、更高的寬高比、更小的導孔和通道、更脆弱的結構、以及越來越高的圖案塌陷風險,正在加速市場從塊材工程轉型至選擇性製程的趨勢。
選擇性製程使用特別設計的化學品與材料相互作用,以便精密、準確地沉積及去除目標材料。選擇性沉積是原子級的加法製造,僅將原子放在需要的地方。選擇性去除是原子級的減法製造,僅去除不需要的原子-即使是那些不在視線內的原子-且其餘原子也會保留在原位。選擇性蝕刻與沉積技術可用於建立並塑造微小的圖案;製造新穎的結構;並克服了技術障礙,例如濕製程導致的圖案塌陷、圖案化過程中的邊緣放置誤差、以及電晶體接點與導線電阻的相關 2D 微縮問題。
Applied leads the industry in selective deposition and selective epitaxy processes. The Endura Copper Barrier Seed IMS™ replaces standard high-resistance via interfaces with a low-resistance selective ALD barrier to enable interconnect metallization for 3nm and beyond. Similarly, the Endura Volta Selective W CVD system replaces conventional metal and dielectric liners and barriers with selective Tungsten deposition to lower contact resistivity and reduce the bottleneck of 2D scaling. The Endura Volta CVD Cobalt system provides a robust seed layer for copper lines and selective Cobalt cap to strengthen adhesion at the copper-dielectric interface. Finally, the Centura Prime Epi system plays a critical role in strain engineering Si-Ge channel performance found in FinFET and GAA transistors.