3D NAND Anatomy
3D NAND, also known as vertical NAND (V-NAND), is a type of non-volatile flash memory, where the cells are stacked vertically to increase storage density. Today’s 3D NAND die is around 12mm x 6mm, depending on its density. A conventional 3D NAND architecture has a cell array with staircase and peripheral transistors next to it.
A 3D NAND cell has multiple components:
- W/TiN for the gate electrode
- AlO and blocking oxide, which controls the bandgap and blocks electron movement
- Silicon nitrate trapping layer which can store electrons
- Tunneling oxide
- A polysilicon channel at the center that makes the electrical connection across the string of memory cells
Lateral Scaling
Lateral scaling requires reducing the staircase area, peripheral circuit area and slit areas. The role of a staircase is to act as a pad for the gate electrode contact. By placing more contacts in the width direction rather than the length direction, manufacturers can save on the overall staircase length. This zig-zag staircase formation brings challenges, such as the need for a deeper etch with profile control as well as maintaining critical dimension (CD) and etch rate uniformity. Today, memory manufacturers prioritize these types of staircase innovations and Applied Materials’ Sym3 has already been adopted for this purpose, continuing our leadership position in staircase etch.
Another opportunity for lateral scaling is in the peripheral CMOS area. Manufacturers are moving the peripheral transistors to either under or over the memory array, targeting around a 10-15% die area savings. The primary benefit of CMOS under array (CuA) is that it has a lower manufacturing cost and yield loss. However, the CMOS junction in CuA must be fabricated before the cell formation. Compared to CuA, the CMOS transistor in CMOS over Array (CoA) must be fabricated on a separate silicon wafer. Subsequently, the two wafers must be bonded to connect the critical metal connection pads.
Vertical Scaling
The second approach to 3D NAND scaling is in the vertical direction. This is accomplished by adding more pairs, but this becomes less cost effective as the height and the aspect ratio increase. Shrinking the thickness of each pair allows more layers at the same stack height. But in shrinking the stack height, it gets progressively difficult to remove the silicon nitrate and to fill the space with metal in the replacement gate process.
With added pairs, thicker hard mask deposition and etch are needed for post-processing. Ironically, a thicker hard mask increases the overall stack height, resulting in a higher aspect ratio. In order to resolve this issue, Applied Materials has more selective and low-stress hard mask films compared to conventional hard mask, which enables the hard mask to be thinner.
After the staircase formation, the etched-out area must be filled with dielectric films. This is done with Applied Materials’ Plasma Enhanced High Aspect Ratio Process or PE-HARP dielectric gap fill process. This film has a very high deposition rate with tunable stress and also exhibits the lowest shrinkage postprocess compared to the alternatives.
The next key process for vertical scaling is metal gap fill for high aspect ratio contact. In 3D NAND, CVD tungsten (W) is widely used to make many connections in the vertical direction. With an increase in the stack height, this metal fill process faces two challenges. First, the deep contacts have a barrel-shaped profile. When the contacts are filled with W, the contact can be pinched off at the top, trapping corrosive gas inside, which can damage large parts of the die afterwards. Second, these metals typically grow with a high tensile stress, which can deform the wafer and crack adjacent delicate features. To address these challenges, Applied Materials pioneered Seam Suppressed Tungsten technology. This process includes a nucleation and treatment step that suppresses the film growth on the top and allows more uniform, seamless bottom-up filling.