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In today’s data driven world, the need for memory is growing at an accelerating pace. From billions of mobile devices to millions of server farms across the world, hundreds of exabytes (1 exabyte = 1 x 1018 bytes) of data is generated daily. This data must be stored in memory in order to be processed and consumed in our everyday lives.
The memory market is led by two types – dynamic random access memory (DRAM) and NAND – working together in a system but for different reasons. Nothing compares to DRAM in random access performance and endurance, while nothing compares to NAND in cost per bit. At one point, the DRAM and NAND markets surpassed $124B combined compared to the $0.5B emerging memory market.
Dynamic random access memory (DRAM) is a major computer component and where the processor goes to quickly store information needed to perform the billions of calculations that it makes every second. A typical DRAM chip has three major areas: the cell array, where the individual bits are stored in tiny capacitors; the logic or core area, where devices such as sense amplifiers and word line decoders help determine how data is accessed from the cell array; the third area is the periphery, which forms the communication links in and out of the DRAM chip. All three areas must scale to meet the industry’s ever-increasing DRAM performance requirements. These scaling challenges can be summarized as maximizing the charge that can be stored in the capacitor, reducing sense amplifier variability, and reducing power losses due to the wiring in the circuitry.