by Nirmalya Maity, Ph.D.

Apr 16, 2020

The Internet of Things (IoT), Big Data and AI are exerting new demands on performance, power, area-cost and time-to-market (PPACt) that exceed the bounds of classic Moore’s Law scaling. This is spurring a combination of approaches that Applied calls the “New Playbook.” A key pillar of the playbook is advanced packaging, which is shorthand for heterogenous design and integration of what can be a wide array of similar or dissimilar chips. Designers can now integrate CMOS chips of various nodes and wafer sizes with other functions including power, RF and photonics. They can combine silicon sourced from different IDMs and foundries to create heterogeneous chips, subsystems or highly integrated systems. In short, it’s about enabling new levels of design and manufacturing flexibility to address chip PPACt.

Recently, several of my colleagues posted blogs about an outstanding panel discussion held at the most recent IEEE International Electron Device Meeting (IEDM) in San Francisco. Titled, “The Future of Logic: EUV is Here, Now What?,” the panel was hosted by my colleague Regina Freed and featured experts from Facebook, IBM Research, Intel, Stanford University and TSMC. I’ll highlight the panelists’ perspectives on heterogeneous design and advanced packaging and share some of the innovative work Applied is doing in this area to help enable the next decade of progress in logic.

The panelists discussed two megatrends that can benefit from advanced packaging: cloud computing and 5G. Hyperscale computing architects are looking for new ways to enable higher performance at constant or lower power. 5G infrastructure and device designers also prioritize signal integrity, form factor, thermal dissipation and cost. 

Heterogeneous design and advanced packaging offer new ways beyond 2D scaling to achieve the optimizations engineers are looking to achieve. Functional system blocks that don’t demand leading-edge nodes can be fabricated on trailing-node geometries, potentially re-using existing logic designs. This can reduce silicon cost, shorten design time and accelerate time to yield and market, which are key benefits to establishing leadership in promising new markets. Additionally, advanced packaging can be used to shorten chip interconnects and reduce parasitics to significantly improve data rates and overall performance.

“I am a big believer in advanced packaging as an enabler of Moore's Law moving forward,” said Ramune Nagisetty, Senior Principal Engineer and Director of Process and Product Integration Technology Development Group at Intel, during the panel. “The future is about specialization at scale with advanced packaging and interoperable chiplets. I foresee that an industry scale ecosystem will evolve around the concept of a chiplet library where you can swap out an older technology node for a new technology node, for example, in high-speed cores. And then you can mix in specialized nodes for specific functionality like power delivery, or memory, or specific types of accelerators like GPUs. This is basically bringing high-resolution fab technology into the advanced packaging arena.”