December 07, 2023


Bala Haran, Ph.D.


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Revisiting the Future of Logic at IEDM 2023

abstract, logic

by Bala Haran
December 7, 2023

For more than a decade, Applied Materials has hosted a technical program during the IEEE International Electron Devices Meeting (IEDM) – the premier conference for reporting breakthroughs in leading-edge semiconductor transistor technology. After a brief hiatus during the COVID-19 pandemic, we are excited to be back during IEDM 2023 with a thought-provoking panel discussion featuring leading technologists from Google, Qualcomm, Intel, Samsung, TSMC, Synopsys and EV Group. This blog provides a preview of the Applied event and highlights Applied’s papers and conference sessions at IEDM.

Gate-All-Around Is Here, Now What?

At Applied's last panel discussion in 2019, the topic was, “The future of logic, EUV is here, now what?” As it happens, I was honored to share my perspective as one of the guest panelists at this event. I have since joined Applied to lead the IMS™ (Integrated Materials Solution™) team, and I am thrilled to have the opportunity to moderate this year's panel.

There were several key themes that emerged from that discussion in 2019. Even back then, AI was already causing the electronics industry to forge new paths with a heightened set of demands driven by an insatiable appetite for data. Solving critical challenges in transistor performance and interconnect resistance was increasingly requiring new architectures and innovations in advanced packaging. Each of these inflections introduced different material challenges, new approaches to deposition and etch, and placed a premium on co-optimization from materials up to the system level.

In other words, we concluded that it was time for a new playbook for semiconductor design and manufacturing supported by a collaborative innovation process that favors system optimization.

Fast forward to 2023. What has happened since our last panel? We have all witnessed firsthand the acceleration of excitement around AI – and not just Generative AI, but the combination of AI in the cloud and at the edge is fueling a new wave of growth and becoming the key driver of leading-edge logic roadmaps. At the same time, as traditional 2D scaling slows, innovation in 3D architectures is accelerating across multiple vectors – from the device to the system level. Complexity has increased – and not just the complexity of process technologies and device integration steps, but the complexity of the entire process roadmap.

With this backdrop, we are gathering on Tuesday, December 12 to explore the future of logic, but this time there is a slight variation on our theme. Now we hope to answer the question: “Gate-All-Around is here, now what?” Just like EUV, GAA transistors are a disruptive innovation that will bring tremendous benefits to chip designers and manufacturers. But they are not the solution to every challenge on the horizon. What are the innovations – including and beyond GAA transistors – that will continue to drive our industry forward?

We are bringing together a panel of experts to delve into the key transistor, wiring and packaging inflections empowering the logic roadmap, including a look at the benefits these technologies bring to system designers – and the manufacturing challenges that must be overcome to enable high-volume production.

Our panel features technologists from:

  • Google and Qualcomm – representing the system design perspective
  • Intel, Samsung and TSMC – the three leading logic manufacturers
  • Synopsys and EV Group – providing the software and equipment ecosystem viewpoint

This promises to be a thought-provoking discussion, and I hope you will consider joining us. Registration is available here: Applied Materials Panel Discussion during IEDM 2023.

AI Means “Actionable Insights”

Immediately following Applied’s event, IEDM will host its traditional evening panel. This year’s discussion will be moderated by Dan Hutcheson, vice chair of TechInsights, and will feature panelists from Advantest, Applied, IBM, Synopsys and TSMC in a conversation about how AI is changing the semiconductor industry. My colleague Anantha Sethuraman, general manager of strategic programs at Applied, will share some of the ways Applied is using AI and other digital tools to help solve chipmakers’ high-value problems. Applied’s AIx TM platform, which stands for Actionable Insight Accelerator, enables engineers to see into semiconductor processes in real-time, take millions of measurements across wafers and individual chips, and optimize thousands of process variables. The platform leverages Applied’s decades of experience modeling process chambers and combines it with cutting-edge data science to accelerate every stage of the chipmaking lifecycle, from R&D to ramp and high-volume manufacturing.

Integrated Solutions for Wiring

As chipmakers continue to scale to the most advanced process nodes, electrical resistance has become a critical bottleneck to further improvements in chip performance and power. Smaller transistor features require thinner interconnect wires, which increases resistance exponentially. If left unchecked, the wiring resistance can fully negate the benefits of more advanced transistors. In recent years, chipmakers have adopted a new approach to depositing transistor wiring by combining physical vapor deposition (PVD) and chemical vapor deposition (CVD) to create pure tungsten metal contacts. Gaurav Thareja, director in Applied’s Metal Deposition Products group, is the lead author for an IEDM publication that proposes a tungsten integration scheme that enables scaling to the 2nm technology node and beyond. The process includes surface preparation along with PVD and CVD processes in a single, high-vacuum system, followed by chemical mechanical planarization (CMP) to minimize metal dishing and dielectric loss. Ashish Pal, senior engineer in Applied’s modeling and design group, will present this paper at the conference session on Tuesday, December 12.

A Focus on Sustainability

As the foundation of innovation in the AI era, semiconductors are more important to the world than ever, and technology leaders are increasingly seeing the need to decouple the industry’s growth from its environmental impact. For the first time in IEDM history, the conference is hosting a special focus session on sustainability in semiconductor device technology and manufacturing on Wednesday, December 13. During the session, Ben Gross, with Applied’s Sustainability Center of Excellence, will describe some of the new tools Applied has developed for monitoring and modeling our systems’ energy use and emissions impact. Applied’s systems engineering approach to sustainability enables us to estimate the real-world savings that our equipment can enable. By looking at the complete system footprint, using modeling tools to influence product design, and quantifying the savings achievable in a high-volume-production setting, we can help impart dramatic improvements in sustainability throughout the semiconductor manufacturing industry.

IEDM 2023 is shaping up to be another important event for the industry. Applied will be there in full force, and we look forward to connecting with colleagues from across the ecosystem as we collaborate to drive innovation for the future.

Bala Haran, Ph.D.

Vice President, Integrated Materials Solutions


Dr. Bala Haran is Vice President of Integrated Materials Solutions at Applied Materials where he leads a team of device integrators and process engineers focused on identifying and enabling new inflections in logic and memory technology. Prior to joining Applied, Bala was at IBM for 18 years where he led multi-company process and device integration teams focused on CMOS technology development and transfer. He holds a Ph.D. in chemical engineering from the University of South Carolina and has more than 50 peer-reviewed publications and 100 patents granted. 

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