January 27, 2022


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How to Think About Rising WFE Intensity


by Sundeep Bajikar

Jan 28, 2022

Defining WFE Intensity

Wafer fab equipment (WFE) is the market for specialized machines needed to fabricate semiconductor chips. WFE intensity refers to the proportion of semiconductor revenue invested in WFE to enable continued growth.

WFE intensity (%) = WFE ($) ÷ Semiconductor Revenues ($) * 100

WFE intensity increases primarily for two reasons: capacity and complexity. 1) Semiconductor fabs need more equipment to increase capacity so they can process more wafers and meet increasing demand for semiconductors. Conventional thinking is that capacity is the primary driver of WFE intensity. 2) Manufacturers add more wafer processing steps to produce more complex circuitry at higher levels of integration, thereby enabling more capable chips at a lower cost per function.

The Battle of Exponentials and WFE Intensity

Our Battle of Exponentials framework highlights an inflection in the semiconductor industry in the 2015 timeframe, including an inflection in WFE intensity. Between 2000 and 2015, WFE intensity was downward sloping, but it has been climbing since (see Chart 1). Factors contributing to the downslope included 1) the transition from 200mm to more productive 300mm wafer sizes in advanced logic and memory, 2) a consistent cadence of classic Moore’s Law 2D shrinks, and 3) consolidation of semiconductor manufacturing and architectures.


Chart 1: Inflection in WFE Intensity. Source: Applied Materials - Strategy & Market Intelligence.

Wafer Size Limited to 300mm = Higher WFE Intensity

A larger wafer can fit more chips, and the transition from 200mm to 300mm enabled chipmakers to produce 2.25X the number of like-sized chips with each wafer. Accordingly, as more of the semiconductor industry transitioned to 300mm wafers, WFE intensity declined. The industry has fully suspended efforts to develop even larger 450mm wafers, so we don’t expect wafer size transitions to constrain WFE growth in the foreseeable future.

Classic 2D Scaling Not Working Well = Higher WFE Intensity

If wafers aren’t getting bigger, and you can’t get more chips per wafer by shrinking the size of each chip through classic 2D scaling, then you simply need to add more wafers to make more chips. In fact, average die sizes of many kinds of chips is increasing. As a result, we are seeing public announcements of the largest number of new, greenfield wafer fab plans in years—particularly in foundry/logic, in both leading-edge and ICAPS nodes.

Diversification of Computing Architectures = Higher WFE Intensity

When Moore’s Law worked well, computing applications concentrated on one prevailing architecture (x86). Exponential increases in transistor budgets and increasing clock speeds gave system designers and programmers the performance they needed to keep up with most workload requirements, which at the time focused on PCs and servers. As computing applications diversified toward mobility and 3D visual computing—and later to more parallel workloads used to accelerate deep learning (AI) and proof-of-work blockchain (e.g. Bitcoin)—architectures proliferated. Today, high-performance computing (HPC) workloads are a leading driver of WFE investments.

In my next blog post I’ll demonstrate that the combination of higher semiconductor growth and higher WFE intensity is driving a secular step-up in WFE growth.

Tags: WFE, WFE Intensity, Moore's Law, Exponential, AI, deep ultraviolet, High-performance Computing, HPC, Blockchain, ICAPS, Foundry, logic

Sundeep Bajikar

Vice President and Head, Corporate Strategy and Marketing


Sundeep Bajikar is Vice President and Head, Corporate Strategy and Marketing at Applied Materials where he is responsible for shaping Applied’s strategies, including business and financial models related to the future of computing and Net Zero, in addition to tracking and analyzing Applied’s core business performance. He joined Applied in 2017 after spending ten years as a Senior Equity Research Analyst covering global technology stocks including Apple and Samsung Electronics, for Morgan Stanley and Jefferies. Previously he worked for a decade as researcher, ASIC Design Engineer, System Architect and Strategic Planning Manager at Intel Corporation.

He holds an MBA in finance from The Wharton School and M.S. degrees in electrical engineering and mechanical engineering from the University of Minnesota. He holds 13 U.S. and international patents with more than 30 additional patents pending. Sundeep is also author of a book titled, “Equity Research for the Technology Investor – Value Investing in Technology Stocks.”

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