ECD is a rapid and cost-effective method of laying down the bulk of the copper wiring in semiconductor device manufacturing. The wiring is used to create the interconnects that form the electrical circuits. For the circuit to function properly, it is essential that the metal completely fills the features of this wiring (vias and trenches) without seams or voids that would jeopardize electrical reliability and functionality.
ECD is a key process in advanced packaging, including 2.5/3D, ball grid arrays, chip-scale packages, and wafer-level packages for applications such as flip-chip, fan-out, fan-in, and hybrid bonding. While copper is the most common plated metal, gold, nickel, silver, and tin can also be deposited by the ECD process. Further, ECD can create multiple interconnect structures, including bumps, pillars, RDLs, TSVs and pads.
Applied technologies achieve the challenging balance of bottom-up fill and sidewall suppression that produces flawless fill in features smaller than 20nm with aspect ratios greater than 5:1. As device densities increase, dynamic process controls enable uniform deposition across the wafer that is necessary for high device yields.