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Endura® PVD

Today’s 150mm and 200mm PVD challenges focus on depositing thicker, highly uniform, low-temperature films. In the power device market, devices with smaller form-factor and footprint that are capable of switching at high speeds are driving the requirement for advanced heat dissipation technologies such as Al layers in the thickness range of 4µm to more than 10µm. Emerging power applications, MEMS, CMOS image sensors, and packaging technologies, e.g., TSV, are driving PVD development in such materials as silicon carbide (SiC), gallium arsenide, aluminum nitride, indium tin oxide, aluminum oxide, and germanium.

The Applied Endura platform is the most successful metallization system in the history of the semiconductor industry. With its deposition capabilities spanning front-end metallization, e.g., cobalt and tungsten; aluminum and copper interconnect; and packaging applications, e.g., underbump metallization, a vast majority of microchips made in the last 20 years have been created using one of the more than 10,000 Endura systems shipped to date.

The Endura system’s capacity to deposit a wide variety of ultra-pure films with tight control over film thickness, superior bottom coverage, and high conformality is key to the fabrication of leading-edge devices. Able to accommodate up to nine process chambers, including two preclean chambers for native oxide removal, the system offers the flexibility to mix and match chambers to create integrated multi-step process sequences. With the introduction of SiC for high-speed applications, wafer handling requirements for these transparent wafers have become especially demanding. The Endura platform is equipped with enhanced capabilities for handling SiC wafers reliably and carefully from loadlock wafer mapping to clear wafer orientation to wafer placement.

With thousands of Endura systems still in production, many in their original configuration, several hardware improvements are available to improve process performance and tool productivity. For example, throughput bottlenecks at the cool-down chamber can be eliminated by converting Chamber A from pass through to cool-down. Wafer placement errors can be eliminated with EZ LCF, while improving the performance for clamped processes with tight edge exclusions. This feature also eliminates stack-up errors related to multi-chamber process sequences. Many chamber upgrades are also available to improve on-wafer process uniformity and reduce maintenance.