As AI drives demand for advanced logic and memory technologies, the chipmaking roadmap is becoming more complex – opening the door to a growing number of defects that can dramatically impact chip performance and yield. During the 2025 SPIE Advanced Lithography + Patterning conference, Applied Materials convened experts from IBM, imec, Intel, and Samsung to discuss how advancements in process control can help address emerging defectivity challenges in the “angstrom era.”

Electron beam (eBeam) imaging has long been an important tool for examining defects that are too small to be seen with optical techniques. Its ultra-high resolution enables detection of the tiniest imperfections in a sea of billions of nanoscale circuit patterns. Traditionally, optical techniques have been used to find defects, while eBeam is deployed to better characterize these defects. In the emerging angstrom era, chipmakers are increasingly benefitting from eBeam’s superior resolution to identify defects buried deep in 3D device structures.

Key takeaways: The dynamic discussion explored novel technologies that deliver better and faster imaging of buried nanoscale defects, emerging use cases for eBeam in both process development and high-volume manufacturing, the role of eBeam in new areas such as high-bandwidth memory (HBM) and advanced packaging, and how eBeam can enable the transistor roadmap as chipmakers develop next-generation architectures such as forksheets and CFETs. Several key themes emerged:

• Panel moderator Ofer Adan of Applied Materials highlighted the growing need for 3D metrology and inspection tools across logic, DRAM and advanced packaging. “Everything has become three dimensional, so we’re being challenged with buried defects at deeper and deeper depth,” he said, citing new device architectures and higher aspect ratio structures in logic and DRAM, as well as emerging defect challenges in advanced packaging as use of microbumps moves to hybrid bonding. “eBeam is enabling us to scale the roadmap and accelerate the time from R&D to high-volume manufacturing.”
• Samsung’s Younghoon Sohn discussed the evolution of eBeam technology as the chipmaking roadmap has transitioned from 2D to 3D, while noting that new capabilities will be essential as this evolution continues to “4D” and beyond. “The 2D case is very straightforward, just a measurement of the space,” he said. However, for the transition to 3D and beyond, “the important development is high-throughput technology, which is essential for productivity.”
• Luciana Meli from IBM focused on inflections that are driving increased use of eBeam for controlling edge-placement error, a critical challenge in the patterning roadmap. “If you look at the backend minimum pitch required for the scaling roadmap, what you see is that we continue to scale, but at a slower pace,” she said. “What is not slowing down are the edge-placement error requirements.” She noted that eBeam is one of the key tools to help manage edge-placement error, with its unique ability to enable hyper-local process control.
• Kale Beckwitt shared observations from more than two decades on the front lines of defect inspection at Intel. “eBeam has really arrived,” he said. “If I look at the last couple FinFET nodes that we’ve developed, we’ve relied critically on eBeam for a number of gap modes.” While eBeam has proven its value in the technology development stage, Beckwitt sees an emerging need for eBeam in high-volume manufacturing, especially with the transition to Gate-All-Around transistors. “As we look at Gate-All-Around and coming technologies, I think these really tie into the strengths of eBeam.”
• Gian Francesco Lorusso from imec described a “renaissance” in eBeam technology that mimicked the historical resurgence of science and art in the 15th century. “At the end of 2017, there was a reset in the field,” he said. “All of a sudden, we started seeing eBeam used to do things that were not even imagined.” This renaissance was driven by the transistor roadmap, which saw an evolution from planar devices to a 3D FinFET architecture. “It’s a complexity that is growing more and more. And this complexity requires effective ways of measuring not only critical dimensions, but you need to measure three-dimensional information from the tools.”

A picture is worth a thousand words: Below is a selection of photos from the panel.