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Products & Services
Products & Technologies
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Applied Materials invests about $3B/year in R&D to enable semiconductor industry growth.
A critical part of the R&D process is exploring new materials, processes, transistor device architectures, design architectures, packaging and system architectures. Further, Applied Materials believes evaluating the PPACt impact of these innovations at the system level is an important part of the R&D Process. We have built engineering capability and developed a suite of productivity enhancement tools to drive R&D acceleration of Systems to Technology Co-optimization (STCO).
Productivity Enhancement Tools:
Ginestra
Materials-to-Device Optimizer
Ginestra integrates relevant physics, critical to understanding and managing the complexity of materials-to-device co-optimization from materials discovery through device performance, reliability and variability projection. Applied’s design and simulation platform accelerates materials-to-device innovation, providing atomic level insights to improve performance, power, area, cost and time to market.
With Ginestra You Can:
- Accelerate R&D to high-volume manufacturing
- Link materials properties to device performance
- Manage complexity of materials innovation
iDRM™
Design Rule Compiler
The technology challenges in making advanced semiconductor processes work with acceptable yield are immense. These, together with additional design challenges and constraints, result in a huge and complex set of design rules. Developing such rules, capturing them clearly, and ensuring their intent is correctly and accurately embodied in downstream PDKs is a major challenge. The iDRM platform enables easy and clear capture of design rules, managing them and ensuring their implementation accuracy.
iDRM Features and Benefits:
- Graphical design rule entry provides ease of use and clarity
- Design rules can be immediately verified on test data to ensure intent is captured correctly and accurately
- Supports both equation-based and pattern-based rules
- Easy data mining provides complete statistics on actual use of each pattern and design rule in any design
- Enables quick impact analysis of a design rule change on existing design data
SLiC™
Standard Cell Library Compiler
Standard-cell libraries are the essential elements that make up every logic block and sub-system. The library architecture, composition and design quality determine the final power, performance and area of any digital IC product. SLIC enables customers to quickly generate complete standard cell libraries optimized for different design styles and goals - from months to days.
With SLiC You Can:
- Automatically generate DRC-correct layout of library cells from netlist
- Quickly explore the impact of different technology and design choices on your library and design
- Evaluate multiple choices from ground rules all the way to actual designs
- Optimize results for various criteria e.g. routability, area
DRVerify™
DRC Runset Validation
DRC runsets are the final check, or line of defense, against design errors and potential silicon failures that might result in high cost of design respins and disrupted production yield ramp. Therefore, the integrity and correctness of these DRC runsets cannot be overstated. This is especially true for new technology and process design kits (PDK).
With DRVerify You Can:
- Verify DRC runset against design rule intent
- Ensure the runset checks all possible corner cases
- Detect coding errors or inaccuracies
- Discover potential conflicts between seemingly unrelated rules
- Enable rigorous comprehensive regressions tests for every runset change or update