Chamber Matching—Easier Said Than Done
By Kevin Sannes
It seems easy enough: to maximize production of a given product, simply optimize the operating parameters of one “golden” tool and then duplicate them exactly across all the tools in the fleet to obtain perfectly matched performance. However, chamber matching is a prime example of the axiom “easier said than done.” In fact, both the importance and the difficulty of matching multiple chambers are growing as scaling continues below 28nm: margins of error are shrinking and 3D structures are posing additional challenges.
The Need for Matching
As downward scaling has progressed, several trends have impacted device fabrication. Multi-patterning schemes are being employed to extend current lithography. Double patterning is already transitioning to quadruple patterning. Where once the process flow might have been lithography followed by etch, multi-patterning now involves a series of lithography, etch, and spacer deposition steps, each of which can introduce process variation across a fleet and resulting differences in CD, etch depth, or alignment. If uncorrected, the cumulative effect over the entire flow can be a major yield killer. It is therefore critical that every chamber on every system in the fab performs to specification in every process.
Achieving desired yields at advanced nodes is also affected by the trend toward 3D devicesanother major contributor to the substantial increase in the number of process stepsas well as the risk of compounding an error made along the way. For example, tens of layers of dielectrics are deposited in 3D NAND staircase stacks; even nanometer-scale deposition non-uniformity in one of the earlier layers will magnify with each successive one. Similarly, etch processes used in STI and 3D NAND staircase applications are becoming extremely complex, sometimes involving upwards of 80 steps. That in itself represents a huge chamber matching task. The task is magnified even further because these deposition and etch process flows take so long to accomplish. Each chamber’s output can be counted in the low single digits per hour and therefore, a production fab must run hundreds of chambers to meet manufacturing -volume goals. The same issue impacts DRAM etch as growing device density has resulted in a steady increase in aspect ratios.
The Matching Challenge
Chamber matching requires a deep understanding of the tool and the high level picture of the application context in which it operates. Successful matching outcomes involve analysis of a large number of variables that effect on-wafer performance, the ability to identify the key variables which will have the desired impact within the application context, and the creation of the right combination of adjustments for matching the tools in the fleet. All this is also becoming extremely difficult as dimensions shrink. At earlier nodes, the typical goal was to match chamber results to within 5% of each other; at advanced nodes, the goal has become matching to within ½-1σ of the mean of the golden chamber. This level of performance demands exceptionally stringent controls yet is such an infinitesimal margin as to be almost unmeasurable by today’s metrology systems.
The complex nature of solving chamber mismatch means that the fab engineer ideally needs to know everything about the systems, their upkeep, and their environment In reality, it is rare that such comprehensive knowledge is available A multitude of potentially influential parameters converge in a given production system, including individual parts or controls, tool configuration, operation and maintenance procedures, process parameter settings (gases, pressure, temperature, etc.), and recipe software. It can be easy to find many areas of mismatch to investigate. However, in most situations, finding the root cause of the mismatch ends up being a process of guesswork and luck that can entail preventive maintenance work, hardware calibration, recipe tuning, parts replacement, and part swapping between good and bad chambers. To say that it is time-consuming and labor-intensive, with machine downtime creating production bottlenecks, is an understatement. Consequently, fabs often live with the problem by dedicating the mismatched system(s) to less critical processes or continue to run them, knowing that the output will result in less-than-optimum binning. In other instances, automatic process controls are used to compensate for the variation by adjusting recipe step times; however this may only serve to mask the true cause of the chamber mismatch.
The Ideal Solution
Given the many possibilities, determining the potential sources of a mismatch and ultimately identifying the root cause should be a methodical approach leveraging data collection, audits, and in depth process and sensor analysis. These data sets would then be analyzed to identify variations between good chambers and mismatched chambers. Finally, results from the process sensitivity and hardware variation analyses would be used as input to process variation analysis that would rank the top parameters affecting chamber matching.
The above analytical approach eliminates guesswork and efficiently streamlines the process to focus corrective action on the top-ranked parameter(s). Significant time, labor, and materials savings would be realized, down time reduced, and fab productivity and yields enhanced.
Reducing variation on product wafers across a tool fleet is critical to maintaining a high fab yield and productivity. Chamber matching challenges are becoming more exacting as technology scales below 28nm. Foundry, memory, and logic fabs require a detailed methodology, multiple skills, and set of specialized tools for fleet matching to sustain optimum fleet performance.
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