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International Memory Workshop & Leti Workshop
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Date | Presentation | Presenter | Location |
May 14, 2024 | Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vcc_min Scaling | Pratik Vyas | TBD |
Demonstration of High-Growth-Rate Epitaxially Grown Si Channel on 3D NAND vehicle with Memory Functionality | Mahendra Pakala | TBD | |
Self-rectifying Non-volatile Tunneling Synapse: Multiscale Modeling Augmented Development | Bastien Beltrando | TBD | |
Panel Discussion: Advanced Channel Materials for Memory Application | Mahendra Pakala | TBD | |
May 15, 2024 | Invited Talk: Die-to-Wafer Hybrid Bonding Challenges for HBM | Gaurav Mehta | TBD |
IEEE Electronic Components and Technology Conference – Packaging
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Date | Presentation | Presenter | Location |
May 29, 2024 | Signal & Power Integrity Optimization Utilizing Silicon Core Substrate (SCS) | Seann Ayers, Steven Verhaverbeke, Han-Wen Chen, Liu Jiang, El Mehdi Bazizi | TBD |
0.5 µm Pitch Wafer-to-Wafer Hybrid Bonding at Low Temperatures With SiCN Bond Layer | Kai Ma, Nikos Bekiaris, Sesh Ramaswami | TBD | |
A Novel Approach to Low Temperature Bonding Using Single Wafer Thermal Processing System | Masha Gorchichko, Shashank Sharma, Ben Ng, Tyler Sherwood, Yoocharn Jeon, Kun Li, Sarabjot Singh, Evan Iler, Raghav Sreenivasan, Sid Krishnan | TBD | |
May 30, 2024 | Dry Processes to Form Fine Via/Trench and Seed Layer on Advanced Substrate | Wen Xiao, Qin Zhong, Cindy Mora, Anindarupa Chunder, Nicholas Loo, Sik Hin Chi, Cheng Sun, Weihua Qing, Harish V Penmethsa, Craig Rosslee, Jeff Turner | TBD |
Challenges and Innovations in Dual Damascene Polymer RDL With 2 μm Pitch and Beyond | Benjamin Briggs, Roger Quon, Chris Bencher, Ryan Ley, C.C. Chuang, Peng Suo, Andy Chang Bum Yong, Luisa Bozano, Jorge Fernandez, Prayundi Lianto, Niranjan Khasgiwale, Siddarth Krishnan | TBD | |
Integrated Hybrid Bonding System for the Next Generation Advanced 3D Packaging | Raymond Hung, Gilbert See, Ying Wang, Chang Bum Yong, Ke Zheng, Yauloong Chong, Avi Shantaram, Ruiping Wang, Arvind Sundarrajan | TBD | |
Simulation and Metrological Applications for RDL Patterning Development of Glass Substrate | Shih-Hsien Lee, Shih-Hao Kuo | TBD | |
Interactive Presentation: Hybrid Bonding Technology Chemical Mechanical Planarization Process Optimization Using Comprehensive 3D Modeling | Liu Jiang, El Mehdi Bazizi, Gregory Costrini, Prayudi Lianto, Gilbert See, Sefa Dag | TBD | |
Interactive Presentation: A Novel FOPLP Structure With Chip First & RDL First Process for Automotive Chip Application | Fredrick Lie | TBD | |
Interactive Presentation: Glass Panel Process Integrated Low Stress Organic Dielectric RDL Structure | Chien Kang Hsiung, Sarah Wozny, Marvvin L Bernt | TBD | |
Interactive Presentation: 300 nm Pitch W2W HBI for CFET and 3D DRAM Through Module Co-Optimization | Tyler Sherwood, Raghav Sreenivasan, Masha Gorchichko, Amit Prakash, Raghuveer Patlolla, Sarabjot Singh, Yoocharn Jeon, Jason Appell, Ryan Ley, Kun Li | TBD | |
Interactive Presentation: A CMP Process for Hybrid Bonding Application With Conventional / nt-Cu and SixNy / SixOy Dielectrics | Prayudi Lianto, Avery Tan, Joselyn Lie, Patrick Lim, Guan Huei See | TBD | |
May 31, 2024 | Interactive Presentation: Hybrid Wiring Layers for Fine Pitch Integration | Kai Zheng, Gilbert Park, Han-Wen Chen, Steven Verhaverbeke | TBD |
Interactive Presentation: Fabrication and Packaging of a Heterogeneously Integrated, Flexible Quantum Dot Enabled MicroDisplay | Lisong Xu, Kai Ding, Mingwei Zhu | TBD |
IEEE International Interconnect Technology Conference
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Date | Presentation | Presenter | Location |
June 4, 2024 | Breaking Barriers: Innovations in MOL and BEOL Interconnects for Advanced Semiconductor Technology (Invited) | Gaurav Thareja | TBD |
Advanced Black Diamond® for <2nm BEOL Low k Integration | Bo Xie, Rui, Lu, Orlando Trejo, Akansha Singh, Michael Haverty, Lauren Bagby, Kent Zhao, Lakmal Kalutarage, Monika Jamieson, Chi-I Lang, Chandru Ramalingam, Li-Qun Xia | TBD | |
June 5, 2024 | Investigation of the Low Dielectric Constant Properties of SiOx/AlOx Nanolaminate Film (Student Paper) | Investigation of the Low Dielectric Constant Properties of SiOx/AlOx Nanolaminate Film (Student Paper) | TBD |
IEEE Symposium on VLSI Technology & Circuits
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Date | Presentation | Presenter | Location |
June 17, 2024 | Short Course 2: Innovations of Material and Process Engineering in the Angstrom Era for Advanced CMOS Logic Technology | Allen Yeong | TBD |
SEMICON West
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Date | Presentation | Presenter | Location |
July 11, 2024 | Heterogeneous integration of Chipsets into 3D Packages | Jinho An | TechTALKS Stage, Moscone South, Exhibition Level, Room 7 |
International Conference on Atomic Layer Deposition & ALE Workshop
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Date | Presentation | Presenter | Location |
August 5, 2024 | Materials Engineering Driving Next Generation Semiconductor Scaling | Bala Haran | Room Hall 3E |
August 6, 2024 | Industrially Scalable Atomic Layer Deposition of Superconducting Thin Films of Tin on Large Area Wafer Substrates with Applied™ Picosun™ Morpher™ | Shashank Shukla | Room Hall 3 |
August 7, 2024 | Reusable Macroscopic HAR Test Kit Enabling Fast, Routine Characterization of Film Conformality | Jesse Kalliomaki | Room Hall 3A |
Power & Compound Semiconductor International Forum 2024 (SEMICON China)
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Date | Presentation | Presenter | Location |
March 21, 2024 | Accelerating Si, SiC & GaN Power Devices’ PPACt (Power, Performance, Area, Cost, Time to Market) Scaling – 加速 Si, SiC 以及 GaN 功率器件的PPACt (功率,性能,面积,成本,产品上市时间) 技术迭代 | Yi Zheng | Pudong Ballroom 1 |
IMAPS Device Packaging Conference
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Date | Presentation | Presenter | Location |
March 19, 2024 | Materials-Technology Co-Optimization (MTCO) for Inter-Die-Gap-Fill (IDGF) in Heterogeneous Integration of Chiplets (TA1) | Sean Seutter et al. | TBD |
China Semiconductor Technology International Conference
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Date | Presentation | Presenter | Location |
March 17, 2024 | Integrated Module Approach to Solutions in the Specialty Device Market | Michael Chudzik | 3rd Floor Auditorium |
Tailoring the deposition and composition of advanced oxide and SiCN films to deliver the highest bonding energy for fusion and hybrid bonding applications | Zongbin Wang | 5th Floor Yangtze River Hall | |
Novel Etch Solution with Sym3 for Logic BEOL Patterning Etch Applications | Hui Sun | 3rd Floor (3H+3I+3J) |
IEEE Electron Devices Technology and Manufacturing Conference
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Date | Presentation | Presenter | Location |
March 3, 2024 | Logic Technology Roadmap | Gaurav Thareja | East Hall, SuperTHEATER |
March 4, 2024 | ComputLitho – An Indigenous Optical Lithography Simulator with Novel Features | Pardeep Kumar | TBD |
Enabling Next Generation CMOS Scaling Through Materials Engineering and Process Technology | Mehul Naik | TBD | |
Semiconductor Fabs & Sustainability | Neela Ayalasomayajula | TBD | |
March 5, 2024 | GAA Technology Innovations for 2nm Logic node and Beyond | El Mehidi Bazizi | TBD |
Coupling Reactor-scale and Feature-Scale Simulations: ProcessTwin™ for Unit Processes | Rajesh Sathiyanarayanan | TBD | |
Evolution of Maskless Digital Lithography A game-changer for Advanced | Ashwini Aggarwal | TBD | |
March 6, 2024 | e-beam technology innovation for EUV, Gate all around logic and Advance Memory acceleration | Nitin Singh Malik | TBD |
Roughness as an Important Metric for Si and SiGe Epi Growth | Yogendra Yadav | TBD |
SPIE Advanced Lithography
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Date | Presentation | Presenter | Location |
February 27, 2024 | Enabling a superior augmented reality experience with high performance waveguides | Ludovic Godet | Grand Ballroom 220C |
Pattern shaping optimization and applications | Yung-Chen Lin | Room 211B | |
Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes | Michael Shifrin (Israel) | Hall 2 | |
February 28, 2024 | Performance comparison of photosensitive polyimides for high resolution dual damascene schemes for FOWLP packaging applications | Luisa D. Bozano | Grand Ballroom 220C |
Low landing energy as an enabler for optimal contour based OPC modeling in the EUV era, The importance of less damaging and surface sensitive metrology to identify true EUV process monitoring | Ran Alkoken (Israel) | Grand Ballroom 220B | |
Matching in a data-driven world | Mor Baram (Israel) | Grand Ballroom 220B | |
Engineering functional resist underlayers to reduce LWR, minimum cd, and dose for chemically amplified resist, Enabling high resolution pillar patterning using metal oxide resist by functional underlayer design | Sudha Rathi | Hall 2 | |
B-spline and Bézier curvilinear representations: a comparative study | Benjamin Venitucci (France) | Hall 2 | |
February 29, 2024 | New ecosystems of metrology, inspection and test are needed for advanced packaging heterogenous integration | Ofer Adan (Israel) | Grand Ballroom 220B |
International Wafer-Level Packaging Conference
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Date | Presentation | Presenter | Location |
February 14, 2024 | Advanced Bonding Films for 3D Wafer Level Integration | Doug Lee | TBD |
Chiplet Summit
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Date | Presentation | Presenter | Location |
February 7, 2024 | Keynote 1: Applied Materials | Subi Kengeri | Great America Ballroom J |
SEMICON Korea 2024년 1월 31일(수) - 2월 2일(금) COEX(코엑스) | |||
일시 | 발표 | 연사 | 위치 |
1월 31일(수) | S2. Advanced Materials & Process Technology Overlay and Wafer Shape Control in Semiconductor Manufacturing | Pradeep Subrahmanyan | 308, 3F |
2월 1일(목) | MI Forum Novel Technology in Defect Review Enables Yield-limiting-defects Inspection of EUV and 3D Gate-All-Around Smaller and Buried Defects | Sarvesh Mundra | 402, 4F |
2월 1일(목) | S4. Plasma Science and Etching Technology Enabling Dry Etching of sub-10 Nm Features at Cryogenic Temperature | Sumit Agarwal | 307, 3F |
2월 2일(금) | Women-in-Technology Great Place to Work in Career Journey | Jungsun Jessie Kim | 401, 4F |
2월 2일(금) | Meet the Experts! Road to Customer Engineers in the Semiconductor Industry | Bobae Lee | 401, 4F |
Electronics Packaging Technology Conference
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Date | Presentation | Presenter | Location |
December 5, 2023 | Die-to-Wafer Hybrid bonding to address next-gen Electronics Packaging Challenges | Avi Shantaram | Grand Ballroom |
December 5, 2023 | Panel Session 1: Chiplets Integration | Arvind Sundarrajan | Grand Ballroom |
December 5, 2023 | Panel Session 2: Artificial Intelligence for Package Design and Manufacturing | Vincent Dicaprio | Grand Ballroom |
IEEE International Electron Devices Meeting | |||
Date | Presentation | Presenter | Location |
December 12, 2023 | Tungsten Interconnect Resistance Reduction Enabling Energy Efficient and High Performance Applications for 2nm Node and Beyond | Gaurav Thareja et al. | Continental 4 |
December 12, 2023 | Sustainability-Aware Technology Development at Applied Materials | Ben Gross, E. Neville Reyes, S. Kapadia | Grand Ballroom A |
December 12, 2023 | AI: Semiconductor Catalyst? Or Disrupter? | Anantha Sethuraman |
SEMICON Japan
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Date | Presentation | Presenter | Location |
December 13, 2023 | Enabling Semiconductor Scaling through 3D Materials Engineering | Ellie Yieh | East Hall, SuperTHEATER |
SEMICON Europa
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Date | Presentation | Presenter | Location |
November 15, 2023 | Rethinking Automation Culture | Chris Reeves | Executive Forum, Hall B2 |
November 15, 2023 | Continuous Sustainability Improvements in Subfab Operation Using Advanced Communication Capabilities as a Cooperative Effort of Multiple Stakeholders | Andreas Neuber | ICM Munich, Room 14a |
November 16, 2023 | The Road to High Volume Manufacturing: Applied Materials Solutions for Silicon Carbide | David Britz | Executive Forum, Hall B2 |
Presented by Applied Materials: Presentation and Discussions at SEMICON West 2023Wednesday, July 12 | |||
Time | Presentation | Presenter and Role | Location |
8:30am - | Presenter: | Keynote Stage, Room 24, North Lower Lobby | |
10:30am - | Smart Mobility – Meeting The Demands of Affordable Electrification | Panel Moderator: | Smart Mobility Stage, Moscone South |
11:00am - 11:25am PT | Presenter: | Workforce Development Theater, Moscone North, Exhibition Level, Hall F | |
12:35pm - | Presenter: | Smart Manufacturing Meet the Experts Theater, Moscone North, Exhibition Level, Hall F | |
2:00pm - | Panel Moderator: | Smart Mobility Stage, Moscone South | |
2:00pm - | Opportunities from Failure – A Day in the Life of an Engineer | Presenter: | Workforce Development Theater, Moscone North, Exhibition Level, Hall F |
2:30pm- | Presenter: | Moscone North, Exhibition Level, | |
3:05pm- | Presenter: | Moscone North, Exhibition Level, | |
Thursday, July 13 | |||
10:35am - 10:50am PT | Presenter: | Moscone North, Exhibition Level, | |
10:55am - | Presenter: | TechTalk Stage, Moscone South, Exhibition Level, Room 4 | |
1:30pm - | Die-to-Wafer Hybrid Bonding to address Next-Gen Electronics Packaging Challenges | Presenter: Avi Shantaram, Business Development & Kinex Global Product Director, Advanced Packaging | Moscone South, Exhibition Level, |