skip to main content

Interconnect

Interconnects serve as the streets and highways of the integrated circuit (IC), connecting elements of the IC into a functioning whole and to the outside world. Interconnect levels (or metal layers) vary in numbers depending on the complexity of the device and are interconnected by etching holes, called vias. Fabricating these intricate structures is one of the most process-intensive and cost-sensitive portions of chip manufacturing. The interconnect inflection revolves around the growing number of metal layers in devices and the effect that higher wiring densities have had on the evolution of insulating films and the new process steps these have required.

What role does Applied Materials play?

The Applied Materials suite of technologies encompasses every process required for interconnect fabrication:

  • Insulator (dielectric) deposition and specialized treatments
  • Dieletric etch to create the trenches and vias to be filled with copper
  • Barrier deposition to prevent copper from diffusing into the dielectric, which can cause shorting
  • Copper seed layer deposition, which facilitates electrodeposition to fill the trenches and vias
  • Electrodeposition of bulk copper
  • Chemical mechanical planarization to remove copper overburden and create a smooth wafer surface for the next step in the fabrication sequence

 

As feature dimensions have shrunk, the widths of the metal lines and the spaces between those lines have shrunk as well. Silicate glass is no longer suitable as an insulating medium. Dielectrics with lower capacitance (or k value) are needed to enable faster device performance and lower power consumption. Over the past several device generations, Applied Materials has developed increasingly porous dielectric films as effective insulators with progressively lower k values. Reducing k value by 0.4—a film generation—reduces the interconnect power requirement by 10%. Applied’s dielectric films have become the industry standard used by fabs worldwide.

The performance of these low-k and ultra-low k films have been enhanced through ultraviolet curing and other post-treatments to optimize their mechanical strength and electrical properties. The films must withstand as many as 150 subsequent process steps, followed by chip packaging procedures. The harsh chemistries and plasmas involved can otherwise cause an undesirable increase in their k value. Innovative treatments developed by Applied strengthen the dielectrics, and electrical testing confirms their effectiveness in lowering the power consumption of the device.

Metallization processes have also encountered new challenges at smaller geometries. The seed layer is created by physical vapor deposition (PVD), a line-of-sight process in which copper is sputtered (or knocked) from a target and onto the wafer. In narrow, high-aspect-ratio features with perpendicular sidewalls, creating uniform seed coverage has become a major challenge, particularly towards the bottoms of the sidewalls. Discontinuities in this layer can lead to yield-limiting voids in the copper fill. At the same time, the higher aspect ratios also raised the risk of defective filling during the electrodeposition process. A long-established leader in PVD, Applied’s most recent innovation in this technology solves the seed layer coverage challenge through a bottom-up fill technique that eases the process requirements of downstream steps by partially filling the feature with copper, reducing the feature’s aspect ratio for electrodeposition. Complementing this advance in seed layer deposition, Applied’s electrodeposition technology delivers void-free copper plating and achieves uniform deposition across the wafer with optimized chemistries.

Chemical mechanical planarization (CMP) opportunity has grown as the number of interconnect levels has increased. Each deposited layer must be polished to ensure a flat surface for subsequent lithography. Without it, the layers would become increasingly uneven and extend outside the depth of focus of available lithography, interfering with the ability to pattern. Not only has copper CMP processing replaced aluminum CMP, but feature size and film thickness have shrunk dramatically. Applied’s innovations have heightened system sensitivity to topography and have integrated performance monitoring that enables exacting control of the planarization process.