IEDM 2010

 
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Applied Materials at IEDM 2010 » December 7 » San Francisco

 
Applied Materials Invites You to Join Us

As conventional scaling approaches its limits, the industry is evaluating alternative channel designs (such as FD SOI, Ge, III-V) alongside 3D multi-gate transistors for achieving the performance, density, reliability, and form factor required in sub-2X logic devices. Will one or both of these approaches overcome the scaling bottlenecks? Can they be cost-competitive? Which application will be first in volume production? How will materials and processes change? And, what alternatives exist if these approaches fail to satisfy performance or cost criteria?

 


Join us as experts from GLOBALFOUNDRIES, IBM, Qualcomm, Samsung and ST discuss this industry challenge.

Click here to register. We hope to see you there!

Customer Reception & Technical Seminar

December 7, 2010
5:15 - 8:00 PM
Wyndham Parc 55 Hotel
Cyril Magnin Street
San Francisco, CA


Panel Moderator
Prof. Yuan Taur, UCSD