每个晶圆的晶体管数量呈倍数增加，降低了单位成本，晶体管尺寸随之缩小，使其速度更快，功耗更低。随着每个晶体管成本下降，制造商现在能以更优化的成本制造功能更强大的芯片，使最终的电子产品更加经济实惠；成本持续下降稳定推动了市场对手机、平板电脑、上网本、视频游戏和 3D 电视等产品的需求，并使这些产品日趋先进。Demand for smart phones and tablets alone is expected to total five billion units over the next four years这些移动设备也将推动强大云端基础设施的发展。未来四年将需要约两亿台服务器才能满足这些移动设备的数据处理需求。这类产品的崛起，将推动新一波的晶体管新技术开发浪潮，也代表着移动时代的来临。
同十年前个人电脑推动处理器和存储器技术的不断进步一样，现在，移动计算也在影响和推动我们客户的技术发展路线。过去，个人电脑的进步是以不断提高处理速度为目标。对于移动设备，技术发展重心已转向延长电池寿命或降低运行功耗，同时，还要满足对于更高功能不断增长的需求。随着半导体器件关键材料的平面 (2D) 缩放逐渐达到极限，移动时代将推动全新 3D 晶体管架构的发展，这需要运用更复杂的技术及各类全新材料。
对设备功能的需求在不断增长，新开发的处理器种类也愈来愈多，包括微处理器、基带处理器，以及将多个处理器核心与图形功能整合的应用处理器。移动时代的全新操作系统愈来愈倚重 NAND 型存储器，在移动设备上的使用甚至已超过了动态随机存储器。
应用材料公司是业界的技术领导者；公司的技术促进了多代 2D 晶体管的尺寸微缩，并将推动向 3D 结构转换。这些技术包括化学气相沉积 (chemical vapor deposition，CVD)、高 k 栅介质/金属栅极物理气相沉积 (physical vapor deposition，PVD)、离子注入、快速热处理 (rapid thermal processing，RTP)、外延生长、刻蚀、平坦化、缺陷检测等。
In processors, the 3D FinFET (fin field effect transistor) is emerging as uniquely suited for low-power operation. Building it will add more than 50 additional single-wafer processing steps to Applied’s served market. Patterning and etching will require exceptional precision to achieve the required fidelity of the fin width and height for billions of transistors. In memory, 3D NAND is a revolutionary new architecture in which all major components of the memory transistor (i.e., the channel, gate stack, and junctions) will be formed horizontally on the wafer. This approach also substitutes the lithography intensity of linear scaling with greater thin-film process intensity, adding more than 30 steps to the current planar sequence to Applied’s served market.
In addition to creating new materials for 3D that behave like those in current 2D technology, the 3D transistor inflection is driving new capabilities in many fabrication processes. Applied Materials’ systems are fulfilling these demands through a variety of innovations. Fabrication sequences will become more deposition-intensive and will require greater conformality of those deposited films, which becomes more challenging as aspect ratios increase. Applied’s most advanced PVD technology achieves the highly conformal coverage needed in metal gate fabrication while its CVD capabilities deliver void-free gap fill in complex topography with demanding feature profiles. Ion implantation now requires much greater energy purity and doping precision without damaging the host material. Applied’s leading-edge cryo-implantation process at wafer temperatures as low as -100˚C is enhancing device performance. And Applied’s unique annealing approach that heats the wafer from the back side optimizes within-die temperature uniformity for dopant activation and other critical material enhancement processes.
Applied’s specialized etch capabilities address the high-aspect ratio “staircase” structures needed for cost-competitive high-volume production of 3D NAND. Planarization systems with exacting real-time process control enable the atomic-level precision required for damage-free polishing of ultra-thin films. Defect inspection and review are vital for optimizing the quality of individual steps in the manufacturing sequence and, ultimately, the production yield. This entails first locating true defects (as opposed to “nuisances” that will not affect the wafer) and then reviewing their composition and root cause. For over a decade as feature and defect sizes have scaled down, Applied has pioneered and enhanced automated defect classification as well as resolution and image quality capabilities, recently achieving resolution of 1 nanometer (1 billionth of a meter) and high quality topographical imaging essential for 3D structures.
The 3D chapter of the transistor story is only just beginning; researchers are actively examining new forms of 3D transistors, their relative costs, and product size. Applied Materials innovations are making it possible to sustain the momentum of transistor evolution for the foreseeable future.
应用材料公司一直是技术领先者，推动了多代平面工艺微缩，在帮助客户向 3D 结构转换方面也走在行业前列。