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The etch process removes selected areas from the surface of the wafer so that other materials may be deposited. “Dry” (plasma) etching is used for circuit-defining steps, while “wet” etching (using chemical baths) is used mainly to clean wafers. Applied also offers an innovative “dry” removal process that selectively removes layers without using plasma. Typically, part of the wafer is protected during the etch by an etch-resistant "masking" material, such as photoresist or a hard mask such as silicon nitride.

Etch processes are referred to as dielectric etch or conductor etch to indicate the types of films that are removed from the wafer. For example, dielectric etch is employed to etch via holes and trenches for metal conductive paths; conductor etch removes polysilicon to create the gate in a transistor, or aluminum and tungsten to reveal the pattern of circuitry in the device structure.

Plasma etching is performed by applying electromagnetic energy (typically RF) to a source gas usually containing chlorine or fluorine. A plasma containing oxygen is used to oxidize ("ash") photoresist and facilitate its removal.The plasma releases positively charged ions that bombard the wafer to remove etch materials and chemically reactive free radicals that react with the etched material to form volatile or nonvolatile byproducts. Highly directional, anisotropic etch produces the almost vertical etch profiles essential for the miniscule features in densely packed chip designs. As scaling continues into single-digit nodes, complex patterning schemes, smaller spaces, more fragile features, higher aspect ratios, and risk of material damage are requiring exceptional selectivity and gentler removal than can be achieved using traditional wet and RIE etch methods. Applied’s plasma-free “dry” removal process employs a radical-based, isotropic process to ensure complete removal of the target material without damaging others. Its unique selectivity between oxide materials of differing densities is a pivotal development in extending the scalability of planar NAND memory and next-generation DRAM devices.

Applied Materials’ etch innovations have consistently met the increasingly challenging requirements of successive inflections, including ever-decreasing device sizes; changes in materials used (such as high-k films or ultra-porous dielectrics); diversification in device architecture (such as finFETs and 3D NAND transistors), new patterning techniques (EUV and multi-patterning using side wall spacers) and new packaging approaches (such as fan-out WLP).