Chamber Matching Reduces Variability Across the Fleet
Maintains High Factory Yield and Output
By Kevin Sannes
High factory yield and output are the foundation of financial performance in a semiconductor fab, and matched performance across all chambers in a fleet is a key mechanism for enhancing factory performance. But the seemingly straightforward process of optimizing the operating parameters on one “golden” chamber and then duplicating them across the fleet has become one of the most challenging issues in advanced fabs. Aggressive matching requirements, variation from multi-patterning, complexity of process recipes, and 3D structures all compound the challenge of achieving and maintaining matched performance on large fleets of chambers.
The Applied Materials FabVantage Consulting team has developed and successfully demonstrated a chamber-matching methodology that streamlines the matching process, shortening the time to root cause. Corrective actions are quickly defined, downtime reduced, and productivity improved.
The Need for Matching
As scaling has progressed below 28nm, new trends are affecting device fabrication productivity. Multi-patterning schemes are being employed to extend current lithography. Double patterning is transitioning to quadruple patterning. Where once the process flow might have been lithography followed by etch, multi-patterning now involves a series of lithography, etch, and spacer deposition steps, each of which can introduce process variation across a fleet with resulting differences in critical dimension (CD), etch depth, or alignment. It is therefore essential that every chamber on every system in the fab perform to specification in every process.
Achieving desired matching at advanced nodes is also affected by the transition to 3D devices, whose fabrication involves a substantial increase in the number of process steps and greater risk of compounding an error made along the way. For example, tens of layers of dielectrics are deposited in 3D NAND staircase stacks (figure 1); even nanometer-scale deposition non-uniformity in one of the earlier layers will magnify with each successive one. Similarly, etch process recipes used in shallow trench isolation and 3D NAND applications are becoming extremely complex, sometimes involving more than 80 steps. High-volume production fabs may need more than 50 chambers for a single process application due to long recipe times and low chamber throughputs. The same issue affects DRAM etch because growing device density has resulted in a steady increase in aspect ratios and recipe complexity.
Figure 1. 3D NAND staircase
The Matching Challenge
Chamber matching requires a deep understanding of the tool design and the process application. Successful matching involves analyzing a large number of variables that influence on-wafer performance, identifying those that have the greatest impact on performance, and prioritizing root causes and required corrective measures. The matching process is becoming extremely difficult as dimensions shrink and CD matching requirements become more aggressive.
At earlier nodes, the typical goal was to match chamber results to within 5% of each other; at advanced nodes, the goal has become matching to within ½–1σ of the mean of the golden chamber—typically on the order of a few angstroms. This level of performance demands exceptionally stringent controls and ongoing performance monitoring.
The complexities of solving chamber mismatch mean that the fab engineer ideally needs to know everything about the systems, their history, and their environment. Rarely is such comprehensive knowledge available. A multitude of potentially influential parameters converge in a given production system, including individual parts and tolerances, chamber configuration, operation and maintenance procedures, process parameter settings (gases, pressure, temperature, etc.), service routines, calibration methods, and system software. In addition, run-to-run (R2R) control adds another complexity, compensating for process variation by adjusting recipe parameters on the fly and masking the underlying causes of chamber mismatch.
It can be easy to find areas of mismatch to investigate. Often though, finding the root cause becomes a process of trial and error that entails preventive maintenance (PM) work, hardware calibration, recipe tuning, parts replacement, and part swapping between good and mismatched chambers.
Efforts to identify and resolve root causes of chamber mismatch are time-consuming and labor-intensive; machine downtime can create production bottlenecks. Fab managers often work around the problem by restricting the mismatched chamber(s) to less critical processes, or by continuing to run them, although they know the output will be less than optimal.
Matching Methodology Trims Time, Cost
To address the complex issue of matching chambers across a fleet, the Applied Materials FabVantage Consulting team has collaborated with process groups and field personnel to develop a methodology that leverages specialized skills and knowledge in data collection, hardware and process audits, and multifaceted analyses. This allows the team to efficiently zero in on the root cause of mismatch, reduce downtime, and improve matching. Their approach has successfully demonstrated time and labor efficiencies and eectively resolved the cause of the mismatch at customer sites. To date, implementation has focused on etch applications; however, the approach is applicable to the full range of semiconductor fabrication processes.
Figure 2 summarizes the FabVantage approach. Skilled engineers perform initial benchmarking of current system performance within a FabVantage 360 assessment, followed by comprehensive hardware and process audits using specialized hardware and software tools. Once hardware variation across the fleet is understood, a process sensitivity experiment is run to determine how each hardware component influences on-wafer performance. Results from the process sensitivity and hardware variation analyses are used to determine the process variation and rank the top contributors to the mismatch. Corrective action to resolve the problems follows this rank order. After the matching problems have been corrected, the final phase focuses on PM execution using monitoring and control of top contributors to maintain chamber matching.
Figure 2. Applied’s FabVantage analytical chamber-matching methodology shortens time to root cause.
Two representative projects illustrate the process and effectiveness of the FabVantage methodology. The first project’s objective was to match CDs and trench depth on 16 etch chambers running 2xnm DRAM production. Each chamber’s CD monthly average was tracked for one high-volume product, for which the customer’s requirement was to achieve a chamber-to-chamber CD range of less than 4Å.
The FabVantage team first quantified the impact of R2R control to identify both on-target chambers and outlier chambers. They performed a comprehensive hardware audit of a selected group of chambers, followed by a process-sensitivity experiment on product wafers using the customer’s production recipe as a baseline condition. Analysis of process-sensitivity tests identified the top 10 parameters influencing CD and trench depth (figure 3). Finally, process-variation analysis prioritized incorrect calibrations of MFC flow and RF linearity as the root causes of the mismatch (figure 4).
Figure 3. Process-sensitivity tests identify the parameters having the greatest effect on CD and trench depth.
Figure 4. Process-variation analysis prioritizes corrective actions.
Corrective work on the systems also revealed two additional contributory factors: intermittent backside helium flow spikes and non-optimal ESC temperature calibration. Consequently, a backside helium tank upgrade kit was installed on all chambers to eliminate the helium delivery issue, and a recommendation was made to improve ESC temperature-calibration accuracy by adopting the Applied Materials best known method (BKM). In parallel with the above audits and data analysis, the team collected sensor data and on-wafer data from the chambers under investigation.
These data sets were merged and correlation analyses performed to determine whether factors other than process variation could be contributing to chamber mismatch (figure 5). These analyses revealed PM variability and an intermittent trench-depth shift, with trench depth correlated to peak-to-peak voltage in a BARC etch step. The FabVantage team made recommendations to address the issues observed with the third-party PM service.
Figure 5. Correlations between sensor and on-wafer data identify factors other than process variation that could contribute to chamber mismatch.
The FabVantage team collected CD data for 30 days to monitor the effectiveness of all corrective actions. With the R2R control effect removed, the calculated range of CDs improved from 22Å to 12Å (figure 6a). Subsequently, the customer’s target CD range of less than 4Å across the fleet was achieved by combining this improvement with R2R control (figure 6b).
Figure 6. (a) Improved chamber matching combined with (b) R2R control reduced CD range from 22Å to customer’s < 4Å target.
The FabVantage team applied the same methodology to the second project, in which 18% of the customer’s chambers were not meeting CD spec for the 2xnm technology node. Not only was CD mismatched, it also drifted between successive PM events.
In this case, process-variation analysis identified ESC temperature calibration, RF source, pressure, and critical gas flows as the top contributors to the mismatch. ESC temperature calibration was corrected and ESC temperature verification was added to the maintenance checklist to ensure ongoing monitoring. CD drift was determined to be the result of a non-optimal in-situ chamber clean recipe; the FabVantage team recommended implementing Applied’s multi-step BKM clean recipe to resolve this issue. Figure 7 illustrates the successful resolution of the CD mismatch and drift using the FabVantage methodology.
Figure 7. CD variation between chambers and CD drift across PM cycle shown on the left are resolved by chamber-matching methodology and BKM.
Reducing variation on product wafers across a tool fleet is critical for high fab productivity. Chamber-matching challenges are becoming more exacting as technology scales below 28nm. To sustain optimal productivity, foundry, memory, and logic fabs require an analytical methodology, multiple skills, and specialized tools for fleet matching. By leveraging Applied’s substantial knowledge base, broad-ranging equipment- and process experience, and proven BKMs, the FabVantage team has successfully demonstrated at customer sites the effectiveness of its analytical approach to matching etch chambers that perform complex fabrication processes. The team is continuing to engage with customers on solving chamber-matching problems for a broader range of applications.
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