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Wafer-Level Packaging

Wafer-level packaging enables rich graphics, high speed, and low-power functionality in mobile, “smart” electronic consumer products. It is also used in fabricating Internet-of-Things devices in automotive, medical, and industrial applications, and is essential for high-performance computing applications. Different types of wafer-level packaging are used in these different market segments.  

WLP schemes involve packaging the chip on the wafer, rather than slicing the wafer first into individual chips and then packaging them. Such schemes deliver greater bandwidth, speed, and reliability; use less power; and offer a wider range of form factors for multi-chip packages used in mobile consumer electronics, high-end supercomputing, gaming, artificial intelligence, and  Internet-of-Things devices. WLP has enabled the industry to evolve beyond wire-bonding to flip-chip packaging, 2.5D interposer, and TSV technology, and most recently to high-density 2D and 3D fan-out schemes. Today, no single WLP scheme is considered standard by the industry. Different schemes are used based on the relative importance of form factor, cost, power consumption, performance, and reliability.

Before WLP, wire-bonding connected chips to a substrate using wires attached to the edges of the chip. Only so many wires could fit around the chip, limiting its data transfer capacity. The wires were also relatively long, which created a timing lag and wasted power. Over the years, as circuits scaled down in accordance with Moore’s Law and these wires became smaller in diameter and closer together, wire-bond transitioned to flip-chip packaging. This scheme replaces wires with ‘bumps’ (i.e., interconnection points or pads) all over the top surface of the wafer to increase the areal density of electrical connections. When the wafer is diced, the chips are turned over and attached to a substrate using copper pillars.

As chips’ inputs/outputs increase, greater interconnect density is needed. A redistribution layer (or RDL) containing conductive metal lines can be used to reroute connections on the chip’s surface. The RDL also enables combination of different chip functionalities in what is called a “system in package” (SiP), commonly present in mobile phones.  A SiP performs all or most of the functions of an electronic system. SiP chips can be stacked vertically or tiled horizontally; they are connected with bumps or wire bonds. In these various layouts, however, wires are millimeters in length, limiting the data-carrying bandwidth and consuming more power than desired for some applications.

By stacking chips and using vertical interconnects running through them, more bandwidth and less power consumption can be achieved. This TSV technology can also be used to connect chips on the same plane using a silicon interposer that is connected to a substrate through copper pillars. A silicon interposer has TSVs running vertically and multiple layers of dense copper interconnects running horizontally. This technology, called 2.5D, can be used in servers, gaming consoles, image sensors, and other high-performance systems. When TSV-enabled chips are stacked on top of each other and interconnected with bumps (and RDL, if necessary), they form 3D integrated chips. TSV can be used for stacked DRAM, stacked NAND, or a processor-DRAM stack in mobile applications.

FOWLP is an alternative to TSV; it is emerging in the industry as a more economical way of achieving high densities of interconnects in compact spaces, allowing for thinner packages and a greater range of form factors.  In FOWLP, single chips are reconstituted into an artificial wafer, made of low-cost polymeric material, with additional space between them for interconnects.  An RDL re-routes the connections on the chip to the peripheral regions.   Benefits of FOWLP include improved performance per watt and a wide range of form factors.