每個晶圓的電晶體數量呈倍數增加降低了單位成本，電晶體尺寸隨之縮小也使速度加快並使功耗減少。隨著每顆電晶體的成本下降，製造商能夠以消費者更容易負擔的成本來製造功能更強大的晶片；成本持續的下降穩定推動了市場對手機、平板電腦、電玩遊戲和 3D 電視等產品的需求，並使這些產品更臻成熟。Demand for smart phones and tablets alone is expected to total five billion units over the next four years. 這些行動裝置也將推動強大雲端基礎設施的發展。未來四年約需二億個伺服器，才能處理這些行動裝置的資料。這類產品的崛起將推動最新一波的電晶體新技術開發，也代表著行動年代來臨了。
如同十年前個人電腦推動處理器和記憶體不斷進步；現在，行動運算正推動用戶技術的發展藍圖。過去，個人電腦的進步是以不斷提高處理速度為目標。在行動裝置方面，技術發展重心已轉向加長電池壽命或降低使用時的電力損耗，同時，還要滿足不斷提升功能的需求。在舊有二維 (2D) 晶體材料微縮方式已達極限情況下，行動時代順勢推動全新的 3D 電晶體架構，運用更複雜技術及各類全新材料。
為因應設備功能需求不斷地增長，新開發的處理器種類也愈來愈多，包括微處理器、基帶處理器，以及將多個處理器核心與圖形功能整合的應用處理器。行動時代的全新作業系統愈來愈倚重 NAND 型記憶體，甚至超越行動裝置中的動態隨機存取記憶體。
應用材料是業界的技術領導者；該公司的技術促成了多代 2D 電晶體微縮技術，並推動 3D 結構的技術轉換，這些技術包括化學氣相沉積 (chemical vapor deposition，CVD)、高介電/金屬閘極物理氣相沉積 (physical vapor deposition，PVD)、離子植入、快速升溫製程處理 (rapid thermal processing，RTP)、磊晶、蝕刻、平坦化、缺陷檢測等。
In processors, the 3D FinFET (fin field effect transistor) is emerging as uniquely suited for low-power operation. Building it will add more than 50 additional single-wafer processing steps to Applied’s served market. Patterning and etching will require exceptional precision to achieve the required fidelity of the fin width and height for billions of transistors. In memory, 3D NAND is a revolutionary new architecture in which all major components of the memory transistor (i.e., the channel, gate stack, and junctions) will be formed horizontally on the wafer. This approach also substitutes the lithography intensity of linear scaling with greater thin-film process intensity, adding more than 30 steps to the current planar sequence to Applied’s served market.
In addition to creating new materials for 3D that behave like those in current 2D technology, the 3D transistor inflection is driving new capabilities in many fabrication processes. Applied Materials’ systems are fulfilling these demands through a variety of innovations. Fabrication sequences will become more deposition-intensive and will require greater conformality of those deposited films, which becomes more challenging as aspect ratios increase. Applied’s most advanced PVD technology achieves the highly conformal coverage needed in metal gate fabrication while its CVD capabilities deliver void-free gap fill in complex topography with demanding feature profiles. Ion implantation now requires much greater energy purity and doping precision without damaging the host material. Applied’s leading-edge cryo-implantation process at wafer temperatures as low as -100˚C is enhancing device performance. And Applied’s unique annealing approach that heats the wafer from the back side optimizes within-die temperature uniformity for dopant activation and other critical material enhancement processes.
Applied’s specialized etch capabilities address the high-aspect ratio “staircase” structures needed for cost-competitive high-volume production of 3D NAND. Planarization systems with exacting real-time process control enable the atomic-level precision required for damage-free polishing of ultra-thin films. Defect inspection and review are vital for optimizing the quality of individual steps in the manufacturing sequence and, ultimately, the production yield. This entails first locating true defects (as opposed to “nuisances” that will not affect the wafer) and then reviewing their composition and root cause. For over a decade as feature and defect sizes have scaled down, Applied has pioneered and enhanced automated defect classification as well as resolution and image quality capabilities, recently achieving resolution of 1 nanometer (1 billionth of a meter) and high quality topographical imaging essential for 3D structures.
The 3D chapter of the transistor story is only just beginning; researchers are actively examining new forms of 3D transistors, their relative costs, and product size. Applied Materials innovations are making it possible to sustain the momentum of transistor evolution for the foreseeable future.
應用材料一直是技術領先者，推動了多代二維晶體的微縮，共且帶領客戶轉換使用 3D 技術。