Integrating these chambers on a single cluster tool is essential for fabricating high-performance transistors at the 22nm and 14nm nodes. The dielectric gate stack is the core of the transistor and is electrically very sensitive to variation and quality. At each logic technology node reduction, the interface-to-bulk ratio increases dramatically, making elimination of queue time ever more crucial to avoid thickening of the interface layers. Also, during air breaks, molecular contaminants (e.g., C, N, O, F, S) can be incorporated into the gate stack interfaces. Integrating the process chambers onto a single vacuum mainframe is the surest way of minimizing these issues and ensuring repeatable, high-quality performance.