skip to main content

Centura® 整合閘極堆疊系統

高介電常數/金屬閘極電晶體中,介電堆疊是由介面氧化層和本體高介電常數層組成。

Centura 整合閘極堆疊系統介紹

堆疊的厚度必須隨著各個節點縮減,符合不斷縮減的等效氧化層厚度 (EOT),以達到元件期許的效能。尺度微縮至 22 奈米以下時,需採用原子層沉積 (ALD) 方能達到超薄的高介電常數薄膜層。為了更進一步縮減等效氧化層厚度,需採用電漿氮化,將控制劑量的氮加入堆疊中,接著需進行退火,穩定加入的氮原子。

此系統包含一個原子層沉積二氧化鉿 (HfO{0}) 沉積反應室以及用於介面層氧化成形、高介電常數層後氮化、氮化後退火的專用反應室。
奈米尺度電晶體閘極工程的挑戰

Integrating these chambers on a single cluster tool is essential for fabricating high-performance transistors at the 22nm and 14nm nodes. The dielectric gate stack is the core of the transistor and is electrically very sensitive to variation and quality. At each logic technology node reduction, the interface-to-bulk ratio increases dramatically, making elimination of queue time ever more crucial to avoid thickening of the interface layers. Also, during air breaks, molecular contaminants (e.g., C, N, O, F, S) can be incorporated into the gate stack interfaces. Integrating the process chambers onto a single vacuum mainframe is the surest way of minimizing these issues and ensuring repeatable, high-quality performance.