Transistor

Multiplying the number of transistors per wafer reduced their unit cost; the accompanying downscaling in transistor dimensions also made them faster and less power-consuming. Chips with greater functionality could be fabricated at a cost that made consumer end products readily affordable; sustaining this decrease in cost has steadily fueled the growing sophistication of, and demand for, such products as mobile phones, tablets, video games, and 3D TV. Demand for smart phones and tablets alone is expected to total five billion units over the next four years. These mobile units will also drive development of a strong cloud infrastructure. Almost 200 million servers will be needed in the next four years to manage the data from these mobile devices. For the transistor, the rise of these types of products marks the next wave of technology - the mobility age.

Much like the personal computer drove technology for processors and memory a decade ago; mobile computing is driving today’s customer technology roadmap. In the past, advances for the personal computer aimed at continually increasing processing speed. For mobile devices, the focus shifts to extending battery life, or lower-power operation, while satisfying the ever-increasing demand for enhanced functionality. With historical planar (2D) scaling of critical materials approaching its limit, the mobility age is driving new 3D transistor architectures that involve more complex technologies and a range of new materials.

Processors are proliferating as device functionality grows—microprocessors, baseband processors, and application processors that integrate multiple processor cores with graphics functionality. The new operating systems for the mobility age rely increasingly on NAND-based memory, which has overtaken dynamic random access memory in mobile devices.

In processors, the 3D FinFET (fin field effect transistor) is emerging as uniquely suited for low-power operation. Building it will add more than 50 additional single-wafer processing steps to Applied’s served market. Patterning and etching will require exceptional precision to achieve the required fidelity of the fin width and height for billions of transistors. In memory, 3D NAND is a revolutionary new architecture in which all major components of the memory transistor (i.e., the channel, gate stack, and junctions) will be formed horizontally on the wafer. This approach also substitutes the lithography intensity of linear scaling with greater thin-film process intensity, adding more than 30 steps to the current planar sequence to Applied’s served market.

In addition to creating new materials for 3D that behave like those in current 2D technology, the 3D transistor inflection is driving new capabilities in many fabrication processes. Applied Materials’ systems are fulfilling these demands through a variety of innovations. Fabrication sequences will become more deposition-intensive and will require greater conformality of those deposited films, which becomes more challenging as aspect ratios increase. Applied’s most advanced PVD technology achieves the highly conformal coverage needed in metal gate fabrication while its CVD capabilities deliver void-free gap fill in complex topography with demanding feature profiles. Ion implantation now requires much greater energy purity and doping precision without damaging the host material. Applied’s leading-edge cryo-implantation process at wafer temperatures as low as -100˚C is enhancing device performance. And Applied’s unique annealing approach that heats the wafer from the back side optimizes within-die temperature uniformity for dopant activation and other critical material enhancement processes.

Applied’s specialized etch capabilities address the high-aspect ratio “staircase” structures needed for cost-competitive high-volume production of 3D NAND. Planarization systems with exacting real-time process control enable the atomic-level precision required for damage-free polishing of ultra-thin films. Defect inspection and review are vital for optimizing the quality of individual steps in the manufacturing sequence and, ultimately, the production yield. This entails first locating true defects (as opposed to “nuisances” that will not affect the wafer) and then reviewing their composition and root cause. For over a decade as feature and defect sizes have scaled down, Applied has pioneered and enhanced automated defect classification as well as resolution and image quality capabilities, recently achieving resolution of 1 nanometer (1 billionth of a meter) and high quality topographical imaging essential for 3D structures.

The 3D chapter of the transistor story is only just beginning; researchers are actively examining new forms of 3D transistors, their relative costs, and product size. Applied Materials innovations are making it possible to sustain the momentum of transistor evolution for the foreseeable future.