Packaging

What is wafer-level packaging and what issues does it solve?

The term describes processes performed at the wafer level (not die level) that deliver greater bandwidth or data handling capacity, using less power, in smaller and smaller end products. These processes have enabled the industry to evolve beyond wire-bonding to flip-chip packaging and through-silicon via (or TSV) technology.

In wire-bonding, chips are connected to a substrate using wires attached to the edges of the chip. Only so many wires can fit around the chip, which limits its data transfer capacity. Also, the wires are relatively long, which creates a timing lag and wastes power along the way. These wires have been getting smaller in diameter and closer together, which has stimulated a transition from wire-bond to flip-chip packaging. This transition has accelerated significantly as technology has scaled from 45nm to 28nm to 20nm.

In flip-chip packaging, wires are replaced with ‘bumps’ (i.e., connection points or pads) all over the top surface of the wafer to increase the areal density of electrical connections. When the wafer is diced (or cut up into pieces each containing a chip), the chips are turned over and attached to a substrate.

Where connectivity still poses a challenge, a redistribution layer (or RDL) containing conductive metal lines is also introduced to reroute connections on the die surface. The RDL also enables combination of different die functionalities in what is called a “system in package.”

In spite of these packaging approaches, however, when chips are placed and inter-connected on a board, they are connected by wires that are millimeters in length. This still limits the data-carrying bandwidth between them. And power consumption is still higher than is desirable.

Here is where TSV technology comes in. In TSV, vertical interconnects are running through the dies. This technology is used to connect chips on the same plane using a silicon interposer. A silicon interposer has TSVs running vertically and multiple layers of dense copper interconnects running horizontally. This technology, colloquially called 2.5D, can be used in servers, gaming consoles, and other high-performance systems. When TSV-enabled die are stacked on top of each other and interconnected with bumps (and RDL, if necessary), they form 3D integrated chips. This technology can be used for stacked DRAM, stacked NAND, or a processor-DRAM stack in mobile applications. TSVs have replaced peripheral wires that are millimeters in length with vertical connections that are just microns in length (1,000 times shorter).

These composite high-performance chip packages can be made from chips fabricated at the most cost-effective process node. They contain thousands, not hundreds, of inter-chip connections, enhancing their bandwidth. Connections are now microns long and are situated over the entire area of the chip, enabling faster data exchange and lower operating power.

In summary, TSVs offer all the attributes needed for today's mobile devices and cloud computing servers–greater functionality, faster operation, lower power consumption, longer battery life, and smallest volume. The dramatically increased bandwidth of multiple memory chips closely linked to multi-core central processing units demolishes the memory wall.

In addition, we have optimized the unit processes performed by our systems and have completed early cycles of learning on integrated process flows at our Maydan Technology Center in Sunnyvale, California. We are extending our work in this area with our new advanced packaging laboratory in Singapore.

On a broader scale, we have taken the lead in advancing collaboration between materials and equipment suppliers especially in new unit processes. We also work with R&D consortia to qualify an end-to-end process flow that offers the most cost-effective approach to commercializing TSV technology and accelerates our customers’ time to market. Within this framework of collaboration, Applied Materials will continue promoting the development of future wafer-level packaging technologies.

We’ve seen dramatic advances in only a few years. The power of a large computer just a few years ago is packed into a smartphone today. Mobile entertainment has become ubiquitous. And the story is far from over. Each time we think we are reaching the limits of technology, another breakthrough occurs. Wafer-level processing for packaging is one of the critical technologies that will keep the innovations coming for many years to come.