Wafer-Level Packaging

An emerging area for Applied's technology is in three-dimensional integrated circuits (3D-ICs), a type of chip packaging done at the wafer level to streamline the manufacturing process. In a 3D-IC, multiple chips are vertically stacked in a single package to deliver higher performance and functionality in a smaller area. The chips are electrically connected using deep holes called through-silicon vias (TSVs).

TSV Fabrication

Applied has a full line of production-proven systems and processes required for TSV manufacturing and is leading the efforts, working with consortia and other equipment suppliers, to enable its adoption.

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Bump Technology

Applied is also working with customers on conventional wafer-level packaging technology where the connections between chips are made using external wires or with "flip chip" technology. In flip chips, solder "bumps" are deposited on pads located at the top of the die, which is then turned over so the pads align with those on the external circuit.

Because of its flexibility and low cost, bump technology is expected to remain a workhorse technique for many years, enabling chips with different functions and with very different design rules to be combined in a convenient cost-effective package. Applied Materials offers chipmakers and packaging specialists high-productivity metallization, dielectric deposition and etch solutions to support flip-chip packaging, including under-bump metallization and redistribution layer applications.

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