Conventional DRAM designs surround each storage capacitor with its control circuitry and address lines. To pack more bits onto each chip, leading memory makers are instead burying the address lines underneath the capacitor in the silicon wafer. Applied has met this new design challenge with a full range of manufacturing systems targeted to enable this new approach.
Over the last few device generations, DRAM manufacturers have developed alternative cell layouts that reduce the area they occupy on the chip.
The latest designs allow a 50% increase in density by burying the address lines in the silicon substrate, then fabricating the transistor and capacitor on top to form a vertical stack.
Applied has developed unique technology to enable the high-volume manufacturing of this new memory layout, which requires the manipulation of very complex, deep structures. The Centura Mariana etch system, for example, can etch trenches with aspect ratios in excess of 80:1, while the revolutionary Producer Eterna system deposits insulating films that flow like liquid, completely filling any structure to provide robust, reliable device performance.
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