Conventional DRAM designs surround each storage capacitor with its control circuitry and address lines. To pack more bits onto each chip, leading memory makers are instead burying the address lines underneath the capacitor in the silicon wafer. Applied has met this new design challenge with a full range of manufacturing systems targeted to enable this new approach.
As further scaling of conventional flash memory cells becomes impractical, many leading manufacturers are developing a technology called "3D Stacked NAND." Multiple 2D memory arrays are fabricated on top of each other, thereby multiplying the capacity of the chip without reducing the size of each cell. Applied's innovative systems are helping flash memory manufacturers implement this exciting new technology.