Patterning

Background

In 1975, Gordon E. Moore, co-founder of Intel, observed that the number of components in integrated circuits had doubled every year since the invention of these circuits in 1958. He theorized that they would continue to do so for the next decade. His prediction was adopted by the semiconductor industry as the “roadmap” for research and development for high-volume production and remains true today, thanks in large part to patterning technology. It has enabled manufacturers to progressively scale down critical dimensions of circuits and their components, thereby increasing the functionality produced per unit area of silicon wafer.

Patterning uses the process of photolithography and optical masks to print patterns that guide the deposition or removal of material from the wafer at specific steps in the device fabrication process. At each layer of the device, material is deposited or removed in those areas not covered by the mask and then a new mask is used for the next layer. The wafer is repeatedly processed in this fashion, creating multiple layers of circuitry.

Patterning Evolution

As demands have grown over the years for greater performance from electronic devices, chipmakers have responded by packing wafers with more of the transistors that drive that performance. In other words, patterned dimensions for transistors and interconnects have been shrinking. And as dimensions shrank, greater numbers of circuits could be made on each wafer, which made circuits cheaper while transistors became faster and consumed less power. As the cost per transistor dropped, chips with greater functionality could be fabricated at a cost that made the consumer end product readily affordable; this sustained decrease in cost has steadily fueled the growing sophistication of, and demand for, such products as mobile phones, tablets, netbooks, video games, and 3D TV.

To sustain generations of feature downscaling on the wafer, photolithography itself has had to evolve. Deep ultraviolet photolithographic wavelengths shortened from 248nm to 193nm, and as scaling continued to 45nm and below, immersion lithography replaced “dry” photolithography, enhancing resolution by 30-40% and enabling patterning at dimensions a fraction of the wavelength used in the process. Today, such techniques as double- and quadruple-patterning are being used to extend the resolution of immersion lithography. Double patterning is enabling device scaling to 22nm; quadruple patterning will enable 10nm geometries.

As patterns have become smaller and smaller, masks have become more complex to ensure accurate transfer of the pattern, and etching them has become correspondingly more advanced. Verifying that the mask is defect-free is imperative to avoid costly scrap caused by replicating a mask defect on the wafer, especially in the case of high-revenue-earning chips. With features shrinking and aspect ratios (ratio of diameter to depth) growing, on-wafer processes have had to meet increasingly challenging specifications as well. Optimizing ultimate device performance requires etch processes, for example, to produce precise profiles through a variety of film types, uniform feature width and spacing [known as critical dimension (CD) uniformity], and smooth edges [i.e., no line edge roughness (LER)]. This performance must be replicated with exacting precision over the entire wafer, and repeated on thousands of wafers at a time. When features are 20 atoms wide and spaced 40 atoms apart—as will be the case at the 14nm node—meeting these demands requires extraordinary precision and repeatability control. As transistors transition to 3D designs in the next few years, etch processes will face new requirements for simultaneous multi-depth etching and other complexities.

To make this type of etch precision feasible, photoresist and hard mask materials have been evolving to enhance resolution and provide the robustness necessary to enable advanced patterning in terms of selectivity, profile control, and LER improvement. Thick organic polymer photoresist layers (~500nm) used at the larger geometries a decade ago were gradually replaced by multilayer resists for enhanced strength as the total thickness of the resist decreased by 50% and new resist formulations for 193nm lithography proved fragile and more susceptible to degradation and deformation in plasma. This loss of edge definition made higher feature density and integrity more difficult to achieve, problems that organic and metal hard masks could resolve. Of these, Applied pioneered breakthrough amorphous carbon hard mask technology. More robust and adhesive than photoresist, this family of advanced patterning films (APF) is widely used in the industry for small features and high aspect ratio structures, and is an enabler of Applied’s pioneering development of self-aligned double patterning sequences, which benefit from its high etch selectivity, excellent CD control, and negligible LER. Processes used for filling the vias and trenches that comprise the circuits have also had to evolve to enable defect-free deposition. The challenge faced is that the apertures into which film must be deposited have been shrinking while their aspect ratio has been increasing. In response, chemical vapor deposition has evolved to produce progressively more conformal films. Physical vapor deposition, by which material is deposited by sputtering, has been successively enhanced to achieve the required coverage of the sides and bottoms of the vias, using a thermal process that extends the technology to the 10nm node.

Besides forming these microscopic features, Applied Materials’ processes also preserve their physical integrity. Some restore and strengthen crystal lattice structures that have been weakened by preceding steps in the device fabrication sequence. Others (e.g., oxidation removal) ensure that the surfaces of the feature are pristine for the next step.

Process quality monitoring is the role of Applied Materials’ inspection and analysis systems. As patterning and feature geometries have shrunk, defects that would not have been problematic at earlier technology nodes have become “killer” defects, or substantial yield limiters. Applied has progressively improved resolution and imaging capability of its inspection systems, enabling multi-dimensional imaging and access to a wide range of light conditions. These systems, which can operate in-line with on-wafer processes, examine wafers multiple times during the device fabrication sequence to detect and analyze defects that may have been introduced by a process or another source. They facilitate prompt correction of process conditions or equipment to minimize occurrence of such defects, helping to achieve the customer’s desired yields.