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|An introduction to the Centura|
Integrated Gate Stack system
|Challenges in nanoscale transistor|
In a high-k/metal gate transistor, the dielectric stack is composed of the interface oxide layer and the bulk high-k layer. With each node, the stack thickness must scale down to meet ever decreasing equivalent oxide thickness (EOT) targets to achieve desired device performance. Scaling to 22nm and below requires that atomic layer deposition (ALD) be used to achieve the ultra-thin layer of high-k film. To reduce the EOT further, plasma nitridation is employed to incorporate a controlled dose of nitrogen into the stack, followed by annealing to stabilize the incorporated nitrogen atoms.
The Centura Integrated Gate Stack system with ALD high-k chamber technology for 22nm and below uses Applied’s production-proven Centura Gate Stack platform to deliver the complete high-k process sequence in a controlled high vacuum environment without an “air break”. The system consists of an ALD HfO2 (hafnium oxide) deposition chamber and specialized chambers for interface layer oxide formation, post high-k nitridation, and post-nitridation anneal.
Integrating these chambers on a single cluster tool is essential for fabricating high-performance transistors at the 22nm and 14nm nodes. The dielectric gate stack is the core of the transistor and is electrically very sensitive to variation and quality. At each logic technology node reduction, the interface-to-bulk ratio increases dramatically, making elimination of queue time ever more crucial to avoid thickening of the interface layers. Also, during air breaks, molecular contaminants (e.g., C, N, O, F, S) can be incorporated into the gate stack interfaces. Integrating the process chambers onto a single vacuum mainframe is the surest way of minimizing these issues and ensuring repeatable, high-quality performance.
Ultrathin SiO2 Interface Layer Growth, 18th IEEE Conference on Advanced Thermal Processing of Semiconductors - RTP 2010 (280KB, PDF)
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