In December, Applied Materials hosted “The Future of Strain Engineering, A Technical Symposium” at the Nikko Hotel in San Francisco, bringing together a distinguished panel of senior executives and prominent technology experts to discuss strain engineering for advanced transistors.
This technology represents a critical breakthrough that enables the industry to address performance and power issues without making significant design changes. As transistor dimensions shrink to the 45nm node, scaling alone cannot provide the required performance benefits. New engineering techniques, including SiGe, ultra-high stress films and other methods that produce strained silicon are needed to maintain the pace of innovation described by Moore’s Law.
During the session, the panel explored such questions as:
What does strain engineering look like in 2010?
Does strain postpone the adoption of FinFETs, FUSI or FD-SOI ?
How far can strain engineering extend conventional CMOS scaling?
Local versus global strain: Why is global strain engineering not catching on? Or is it?
Moderated by Dr. Scott Thompson, University of Florida, the panel included:
Carlos Diaz, Deputy Director, Logic Technology Division, TSMC
Tahir Ghani, 45nm Front-End Program Manager, Intel
Francois J. Henley, Chief Executive Officer, SiGen
Judy Hoyt, MIT
Ben McKee, Vice President, TI Fellow Emeritus
Ken Rim, SRDC, IBM
Mark Pinto, Chief Technology Officer and Senior Vice President New Business and New Products Group, Applied Materials
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