Applied Materials offers a host of litho-enabling solutions designed to extend existing lithography equipment for advanced 45nm device fabrication. The unique Applied product portfolio addresses an array of critical applications from OPC qualification, dielectric patterning films, and metal hardmask to pattern transfer, mask etch, and planarity enhancement—each technology carefully engineered to maximize the lithography process window and overall fab economics.
At 65nm and beyond technology nodes, Optical Proximity Correction (OPC) is required to enhance masks’ printability for almost all layers in a chip design. Along with the expanded OPC usage comes the challenge to quickly measure hundreds of sites on a wafer in order to verify that what is printed on the wafer is indeed what the chip designer intended to produce.
OPC Check is a Design-Based Metrology (DBM) application available on the Applied VeritySEM metrology system. It automates the OPC qualification process, reducing mask development time by up to 90% compared to current manual methods. OPC Check takes design data directly from EDA systems, employs a suite of proprietary algorithms to automatically create metrology recipes, then directs VeritySEM to perform thousands of measurements at high throughput and high accuracy. The metrology data is then sent back to OPC Check and the EDA systems where it can be analyzed and used for model building, mask qualification and process window characterization.
| A variety of CVD and PVD films can be used as patterning films, replacing photoresist as the mask in the pattering stack. The advantages versus photoresist-only schemes are numerous: improved etch selectivity, no contamination (no penetration/interaction with underlying structures), and easy strippability (no organic/polymeric residues, potential elimination of damaging ash step). Two that are gaining acceptance at the most advanced technology nodes are amorphous carbon and sputtered TiN. |
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The Advanced Patterning Film (APF) solution is a unique dual-layer patterning film stack that combines strippable CVD carbon hardmask technology with a dielectric anti-reflective coating (DARC) to enable advanced high aspect ratio contact etching and critical sub-40nm gate patterning. The APF/DARC film stack provides <0.5% reflectivity, which is necessary for good CD control, and requires as little as 100nm of photoresist, compared to traditional approaches needing more than 4X the amount for defining the pattern. With its high selectivity to polysilicon and oxide, APF provides exceptional control of the etching process. This APF solution is currently being used for STI, gate, contact, capacitor, bitline, and M1 to provide etch margin, line edge roughness control and low reflectivity in the lithography and etch steps. |
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The metal hardmask integration scheme for copper/low k BEOL pattern transfer is gaining market acceptance as this approach enables chip-makers to use the same hardware set for multiple technology generations. A key benefit of this method is the elimination of undesirable interactions between photoresist and low k dielectric materials, as well as ashing-related low k damage. These advantages help enable the adoption of more advanced low k dielectrics. Using metal hardmask and progressively lower k materials, one can realize better CD and faceting control, both of which are essential for further reducing feature size and increasing packing density.
An alternative to metal hardmasks is a tri-layer approach, in which a dielectric film is used as the hardmask for pattern transfer. Like the metal hardmask approach, this also allows thinner photoresist for wider lithography and enhanced etch process windows. |
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Device manufacturers want the gate CD to be much smaller than the printed dimension to make possible higher performance transistors and the higher revenues they earn. The standard industry technique for shrinking the printed dimension is gate trimming, which is extensively used to extend the life of current lithography technology.
Chemically enhanced photoresist has long been the volume production workhorse for pattern transfer. However, in dark field feature settings, such as via and contact holes, the printed image is always larger than the target. For continued scaling of contact and via holes this drawback poses a major challenge. To fulfill Moore’s Law, one would need to use next-generation lithography tooling for current generation production. Applied Materials solves this dilemma through a highly controllable process of polymer deposition to reduce feature size on the wafer in its advanced dielectric |
| Centura Enabler Etch chamber. Programmable CD reduction of up to 40nm has been demonstrated with no adverse effect on larger structures. This new etch capability will be valuable in extending the useful life of current lithography technology. |
By expending our view of lithography to include both upstream and downstream processes—realizing that patterning is more than printing—Applied Materials has developed extendible solutions to address critical patterning challenges.
News Features, Articles, and Presentations:
Applied's Litho Scheme: Patterning vs. Printing, Aaron Hand, Semiconductor International, April 1, 2007†
Lithography Becomes Big Bottleneck, Ed Sperling, Electronic News, June 2006†
Can we Stay Dry, Applied Materials Press Conference, Feb 2006 (408KB)
Using design intent to qualify and control lithography manufacturing, SPIE Microlithograhy Conference, Feb 2006 (250KB)
Advanced CD-SEM matching methodologies for OPC litho cell-based matching verification, SPIE Microlithograhy Conference, Feb 2006 (734KB)
Introduction of PECVD Carbon Hardmask APF(TM) for sub-90nm DRAM Technology, ECS, 2004 (876KB)
Related Press Releases:
Semiconductor Industry Technologists to Debate 45nm Patterning Issues at Applied Materials' Forum During IITC
Related Events:
Symposium at 2006 IITC - The Patterning Challenge: What Makes Sense for 45nm and Beyond. Panel Participants: Crolles2, IBM, IMEC, TSMC, Albany Nanotech and Applied Materials
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