Applied Materials, Inc. - Breaking the 65nm Barrier

200mm

A size of silicon wafer approximately 8-inches in diameter.

300mm

A size of silicon wafer approximately 12-inches in diameter.

ABATEMENT

A process where toxic or other hazardous substances are removed from a liquid or gas. (e.g. Removing copper particles from CMP slurry.)

ADVANCED PATTERNING FILMS (APF)

A strippable hardmask (an amorphous carbon/DARC stack film) that is designed to replace the spin-on ARC in typical trim procedures.

ALUMINUM CHEMICAL VAPOR DEPOSITION (ALCVD)

A CVD process that results in deposited aluminum on a substrate.

ALUMINIUM INTERCONNECT

Aluminum pathways within a microchip that connect the transistors.

ALUMINUM LOW PRESSURE SEED (ALPS)

Originally an aluminum process, now also used for other metal PVD processes.

AMBIENT CONTROL CHAMBER (ACC)

A chamber that stores and pressurizes in-process wafers. The chamber attaches to the side of the factory interface and is fed by the FI robots.

AMORPHOUS SILICON

A type of silicon deposited on a variety of surfaces (rigid and flexible) with thin homogenous layers. Amorphous silicon absorbs light more effectively than crystalline silicon, so the cells can be thinner. For this reason, amorphous silicon is also known as a "thin film" photovoltaic technology.

ANGSTROM (Å)

A unit of length; one ten-billionth of a meter.

ANNEAL

A high-temperature processing step (usually the last one) designed to repair defects in the crystal structure of the wafer.

ANTI-REFLECTIVE COATING (ARC)

A light-absorbing metal layer (typically titanium nitride), deposited on top of metal or polysilicon, to improve photolithography performance.

ASPECT RATIO

The ratio of depth to width of a via or contact structure.

ATMOSPHERIC PRESSURE CVD (APCVD)

Refers to systems whose deposition environments operate at or near atmospheric pressure. Typically, wafers are placed horizontally on belt-driven flat susceptors which move through the deposition zone. Belt speed and gas flow determine the film thickness.

ATOMIC LAYER DEPOSITION (ALD)

A specialized CVD process required for sub 100nm deposition.

AUTOMATED PROCESS CONTROL (APC)

A computer controller for gas panels used within semiconductor manufacturing.

AUTOMATIC DEFECT CLASSIFICATION (ADC)

Defects found by wafer inspection systems are classified by the system into several categories based on their physical and optical properties.

BACK-END OF LINE (BEOL)

The series of process steps from contact through completion of the wafer, prior to electrical test. Also known as the back-end of semiconductor manufacturing.

BARRIER

A physical layer designed to prevent intermixing of the layers above and below the barrier layer.

BUNNY SUIT

Special clothing worn by people working in clean rooms that reduce the amount of particles that could damage a semiconductor.

CAPACITOR

A device used to store electrical charge in a circuit and smooth out irregular current.

CHEMICAL MECHANICAL PLANARIZATION (CMP)

A process that uses an abrasive, corrosive slurry to physically grind the microscopic topographic features on a partly processed wafer flat (planarization) so that subsequent processes can begin from a flat surface.

CHEMCIAL VAPOR DEPOSITION (CVD)

A process for depositing thin films from a chemical reaction of a vapor or gas.

CHIP

A small piece of a silicon wafer that contains a complete integrated circuit.

CIRCUIT

The combination of many connected electrical elements to accomplish a desired function.

CLEANROOM

The portion of a fab where semiconductors are manufactured. These rooms are strictly monitored to ensure successful manufacturing of semiconductors.

COLOR FILTER

The section of a flat panel display that is broken into areas of red, green and blue. Using a transistor, varying amounts of lights are transmitted through the color filter to create millions of colors.

COMPLIMENTARY METAL OXIDE SEMICONDUCTOR (CMOS)

Any MOS device that incorporates both p-channel and n-channel transistors within the same silicon substrate. CMOS devices are noted for low power requirements, high immunity to electrical noise, and relatively slow speed.

COMPUTER INTEGRATED MANUFACTURING (CIM)

Manufacturing supported by computers. It is the total integration of Computer Aided Design/Manufacturing and also other business operations and databases.

CONDUCTOR

A material that conducts current.

CONTACT

The portion of a microchip that is between the copper or aluminum interconnect and the transistor. This area is often filled with tungsten.

CONTACT DIAMETER

The diameter of the metal structure used to connect the doped contact area formed in the silicon base material to the metal interconnect.

COPPER INTERCONNECT

Copper pathways within a microchip that connect the transistors. Copper interconnects provide better microchip performance when compared to aluminum interconnects.

COPPER SEED LAYER

A thin copper layer deposited by physical vapor deposition over the barrier layer. It acts as a wetting and nucleation layer for growth of the subsequent copper film deposited by electroplating.

CRITICAL DIMENSION SCANNING ELECTRON MICROSCOPY (CD-SEM)

A type of Scanning Electron Microscope used to measure critical dimensions.

CRYSTALLINE

A material that has atoms arranged in an ordered periodic array.

DAMASCENE

An integrated circuit process where a metal conductor pattern is embedded in a dielectric film on the silicon substrate, resulting in a planar interconnection layer. The creation of a damascene structure most often involves chemical mechanical planarization of a nonplanar surface resulting from multiple process steps.

DECOUPLED PLASMA NITRIDATION (DPN)

A method for creating an advanced oxynitride gate dielectric with high nitrogen incorporation at the oxynitride/poly interface and low nitrogen at the Si/oxynitride interface.

DECOUPLED PLASMA SOURCE (DPS)

A technology used within conductor etch that separates the management of plasma density and bias power, resulting in the ability to provide a uniform high ion density over a large process window, maintain a linear plasma density dependence on the inductive RF power and apply a minimum bias power.

DEEP ULTRAVIOLET (DUV)

The portion of the ultraviolet light spectrum with wavelengths below 300nm.

DEFECT INSPECTION

A process where defects are located on a patterned wafer.

DEFECT REVIEW SCANNING ELECTRON MICROSCOPY (DR-SEM)

Classify defect types during the wafer manufacturing process at a very high magnification and determine whether these defects will affect chip yields. DR-SEMs are typically used in the critical layers of the device structure at 0.25 microns and below.

DEPOSITION

A process used to deposit a thin layer of insulating or conductive material onto the wafer.

DESIGN RULES

Rules that outline the allowable dimensions of features used in the design and layout of integrated circuits, such as limits for feature size, and layer-to-layer overlap.

DIELECTRIC

A material that conducts essentially no current when it has a voltage across it: an insulator. Two dielectrics commonly used in semiconductor processing are silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

DIELECTRIC ANTI-REFLECTIVE COATING (DARC)

A non-reflective, non-energy-absorbing, inorganic dielectric layer deposited on top of metal or polysilicon to improve photolithography performance. DARC layers make it possible to accurately transfer the mask pattern onto the photoresist and are typically used in advanced devices such as 256Mb DRAMs and beyond.

DIELECTRIC ANTI-REFLECTIVE LAYER (DARL)

Another name for dielectric anti-reflective coating (DARC).

DIELECTRIC FILM

A non-conducting film. In integrated circuits usually SiO₂ (Silicon Dioxide).

DOPANTS

An impurity added in controlled amounts to a material in order to modify some intrinsic characteristic, such as resistivity/conductivity or melting point.

DOPING

Adding a controlled amount of impurities to a material in order to modify some intrinsic characteristic, e.g., resistivity/conductivity, melting point.

DOUBLE-LAYER METAL (DLM)

The number of metal layers used to personalize an ASIC die.

ELECTROCHEMICAL PLATING (ECP)

A deposition process in which metals are removed from a chemical solution and deposited on a charged surface.

EPI OR EPITAXY

A process technology used in some semiconductor designs where a pure silicon crystalline structure is deposited or "grown" on a bare wafer, enabling a high-purity starting point for building the semiconductor device.

EQUIVALENT OXIDE THICNESS (EOT)

A number used to compare performance of high-k dielectric MOS gates with performance of SiO₂ based MOS gates.

ETCH

A process for removing material in a specified area through a chemical reaction.

ETCH STOP LAYER (ESL)

A layer of film used to identify a place for etching to stop. For example, a nitride layer can be deposited over a poly layer to signal the etch process to stop before etching the poly layer.

FAB

A facility for manufacturing semiconductors.

FACTORY INTERFACE (FI)

An ultra-clean enclosure mounted to the front of a semiconductor processing system that positions wafers or photomasks for subsequent processing.

FLAT PANEL DISPLAY (FPD)

A consumer display device that uses advanced technologies to create televisions and computer monitors. Flat panel displays can be created using thin-film transistors, organic light emitting diodes or plasma technologies.

FLEXIBLE PRINTED CIRCUIT BOARDS (FPCB)

A flexible dielectric substrate having circuit lines attached to one or more surfaces. The flexible printed circuit board is widely used and can be divided into four types according to function: lead line, printed circuit, connector, and integration function system.

FLUORINE-DOPED SILICATE GLASS (FSG)

A reduced dielectric constant (k=approximately 3.5) material made by doping SiO₂ with fluorine.

FRONT-END OF LINE (FEOL)

Front-end processes include: Thermal Processes, Implantation, Chemical Vapor Deposition (CVD), Photolithography, Etching, Physical Vapor Deposition (PVD), Polishing, Process Diagnostics and Control (Metrology), and Cleaning.

GATE

An electrode that adjusts the flow of current in a metal oxide semiconductor transistor.

GATE STACK

The gate/oxide structure in a MOSFET/CMOS.

GEOMETRY

A circuit line or etched feature on a chip.

HARD MASK

A hard nitride layer deposited on top of a polysilicon gate, increasing the adhesion of the resist at edges.

HIGH DENSITY PLASMA (HPD)

A plasma featuring high concentration of free electrons, and hence, high concentration of ions.

HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD)

A type of plasma-enhanced CVD performed under high vacuum and at high plasma excitation voltage in order to improve the ability to fill ultra-small high aspect ratio structures.

HIGH TEMPERATURE OXIDE (HTO)

A high temperature process that deposits an oxide layer on a wafer.

IMMERSION LITHOGRAPHY

A photolithography resolution enhancement technique that replaces the usual air gap between the final lens and the wafer surface with a liquid medium such as water.

IMPLANT

An abbreviation for ion implantation.

INDURIUM TIN OXIDE (ITO)

A transparent, conductive material often used when creating thin-film solar cells.

INSULATOR

Nonconductive dielectric films used to isolate electrically active areas of the device or chip from one another. Some commonly used insulators are silicon dioxide, silicon nitride, boro-phospho-silicate glass (BPSG), and phospho-silicate glass (PSG).

INTEGRATED CIRCUIT (IC)

A fabrication technology that combines components of a circuit on a wafer.

INTERCONNECT

The wiring in an integrated circuit that connects the transistors to one another.

INTERLAYER DIELECTRIC (ILD)

Films used between metal layers of an IC for insulation.

INTERMETAL DIELECTRIC (IMD)

Insulating films used between adjacent metal lines; typically silicon dioxide.

ION IMPLANTATION

A process technology in which ions of dopant chemicals (boron, arsenic, etc.) are accelerated in intense electrical fields to penetrate the surface of a wafer, thus changing the electrical characteristics of the material.

JUNCTION

The interface between two semiconductor regions of differing dopant types. Usually refers to a p-n junction, at which the conductivity semiconductor changes from p-type to n-type.

LATTICE

An orderly arrangement of atoms in the crystal wafer.

LAYERING

A process of depositing thin layers of metal or insulators onto a wafer during the wafer fabrication process using deposition and oxidation techniques.

LINEWIDTH

The width of a metal interconnect.

LIQUID CRYSTAL DISPLAY (LCD)

A type of flat panel display that uses an array of backlit thin film transistors to control a display process.

LITHO ENABLING

A set of processes that enhance the lithography process.

LITHOGRAPHY

The transfer of a pattern or image from one medium to another, such as from a wash to a wafer.

LOAD LOCKS

Isolation chambers that allow a process chamber to be protected from ambient conditions.

LOW K

A dielectric material having relatively greater insulating ability than silicon dioxide (SiO₂), usually with a k<3.5.

LOW PRESSURE CVD (LPCVD)

Low Pressure CVD refers to systems that process wafers in an environment with less than atmospheric pressure. LPCVD systems may be furnaces that process wafers in batches, or single-wafer systems.

MASK

A flat plate that is used to transfer desired geometries for one process layer onto the surface of a wafer.

MATERIAL CONTROL SYSTEM (MCS)

A computer controlled system which controls the flow of physical items in a manufacturing environment.

METALLIZATION

The deposition of a layer of high-conductivity metal (such as aluminum) used to interconnect devices on a chip by CVD or PVD. Metals typically used include aluminum, tungsten and copper, etc.

METROLOGY

The science of measurement to ascertain dimensions, quantity, or capacity; the techniques and procedures for using sensors and measurement equipment to determine physical and electrical properties in wafer processing.

MICRON

(µm or micrometer) A unit of length; one-millionth of a meter or about forty-millionths of an inch. A human hair is approximately 100 microns wide.

MICROPROCESSOR

An integrated circuit that contains the basic arithmetic, logic and control circuitry required for processing.

MONOCYSTALLINE SILICON

A type of silicon that has a single and continuous crystal lattice structure with almost no defects or impurities.

MULTICRYSTALLINE SILICON

A type of silicon that is cast into ingots using grains of monocrystalline silicon. The ingots are then sliced into wafers and used in the manufacturing of microchips and photovoltaic cells.

NANODROPLET™ TECHNOLOGY

A unique nozzle design used in the Applied Tetra Reticle Clean system to create small, uniform, high-momentum droplets that evenly distribute energy and help deliver 32nm-and-beyond cleaning performance.

NANOMANUFACTURING TECHNOLOGY

Solutions for the semiconductor manufacturing industry that are focused on dimensions smaller than 100nm.

NANOMETER

(nm) A unit of length; one billionth of a meter.

NMOS

An n-channel MOS transistor; in an NMOS device the channel is negative during conduction.

NUCLEATION LAYER

A thin layer of film that promotes the growth of the subsequently deposited film.

OPTICAL PROXIMITY CORRECTION (OPC)

A photolithography enhancement technique that modifies photomask circuit features to compensate for the non-ideal properties of the lithography process.

ORGANIC LIGHT EMITTING DIODE (OLED)

A mechanism of light emission where radiation is emitted as a result of electron-hole interactions in a thin film organic semiconductor, leading to the formation of exciton; de-excitatipon of excitons results in photon emission.

PASSIVATION

The final layer in a semiconductor device that forms a hermetic seal over the circuit elements. Plasma nitride and silicon dioxide are the materials primarily used for passivation.

PERFLOUROCOMPOUND (PFC)

A class of gas byproducts created in the manufacturing of semiconductors. PFCs are most commonly seen in CVD processes and can be reduced by an abatement solution.

PHASE SHIFT MASK (PSM)

A conventional mask that phase shifts the light passing through transparent portion of the mask. Phase shifting increases resolution of the pattern transfer with destructive interference, preventing resist exposure in the regions in which it should not be exposed.

PHOTOLITHOGRAPHY

A process by which a mask pattern is transferred to a wafer, usually using a "stepper."

PHOTORESIST

A light-sensitive organic polymer that is exposed by the photolithography process, then developed to produce a pattern which identifies some areas of the film to be etched.

PHOTOVOLTAIC

A process where sunlight is converted to electricity.

PHYSICAL VAPOR DEPOSITION (PVD)

A process technology in which molecules of conducting material (aluminum, titanium nitride, etc.) are "sputtered" from a target of pure material, then deposited on the wafer to create the conducting circuitry within the chip.

PLANARIZATION

The process by which an uneven wafer surface is made relatively flat using a low-selectivity etch.

PLASMA

Ionized gases that have been highly energized—for example, by a radio frequency energy field.

PLASMA DISPLAY PANEL (PDP)

A type of flat panel display where visible light is created by phosphors excited by the discharge of an inert mixture of noble gases (typically neon and xenon).

PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION (PECVD)

A process where plasma is used to lower the temperature required to deposit film onto a wafer.

PMD AND CONTACT

The area of a semiconductor transistor which is made up of the pre-metal dielectric and contact plug.

PMOS

P-channel MOS transistor where the active carriers are holes flowing between p-type source and drain regions in an electrostatically formed p-channel in an n-type silicon substrate. The channel, the source, and the drain are made of a p-type semiconductor material. (HWDI series)

POLYCIDE

A material formed by reaction of polysilicon with a metal.

POLYSILICON

(Poly) Polycrystalline silicon; extensively used as conductor/gate materials in a highly doped state. Poly films are typically deposited using high-temperature CVD technology.

POST NITRIDATION ANNEAL (PNA)

An RTP process used within the creation of the gate stack.

PRE-METAL DIELECTRIC (PMD)

Films that insulate between the wafer and first metal layer.

PROCESS

A group of sequential operations in the manufacturing of an integrated circuit.

PROCESS CHAMBER

An enclosed area in which a process-specific function occurs during wafer manufacturing.

PROCESS INTEGRATION

Optimizing each process step to work correctly with the prior and subsequent steps in a sequential process flow.

RADIO FREQUENCY (RF)

Electromagnetic energy with frequencies ranging from 3 kHz to 300 GHz.

RADIO THERMAL PROCESSING (RTP)

A process in which a wafer is heated to a specified temperature for short periods of time.

RAMAN SPECTROSCOPY

A spectroscopic method of chemical analysis that enables real-time reaction monitoring and characterization of compounds in a non-contact manner.

REACTIVE ION ETCH (RIE)

A combination of chemical and physical etch processes carried out in a plasma.

RETICLE

A flat, transparent plate, used in a stepper, that contains the photographic image of wafer patterns to be reproduced on a wafer.

RF GENERATOR

A device that creates radio frequency, often used to create plasma within the semiconductor industry.

SCANNING ELECTRON MICROSCOPE (SEM)

A device that displays an electronically scanned image of a die or wafer for examination on a screen or for transfer onto photographic film.

SELF-ALIGNED DOUBLE PATTERNING

A "pitch doubling" technique developed by Applied that generates 32nm features using 65nm half-pitch lithography.

SEMICONDUCTOR

A material whose electrical conductivity is intermediate between that of metals (conductors) and insulators (non-conductors) and can be modified physically or chemically to increase or decrease its conductivity from a "normal" state by "dopants."

SHALLOW TRENCH ISOLATION (STI)

The STI isolates each transistor from its adjacent transistor in order to prevent current leakage. Traditionally this isolation was accomplished with a LOCOS (localized oxidation of silicon) field oxide process.

SILANE (SiH₄)

A gas that readily decomposes into silicon and hydrogen, silane is often used to deposit silicon-containing compounds. It also reacts with ammonia to form silicon nitride, or with oxygen to form silicon dioxide.

SILICIDE

A film compound of silicon with a refractory metal. Common silicide semiconductor films (used as interconnects) include tantalum, tungsten, titanium and molybdenum.

SILICON

A brownish crystalline semi-metal used to make most semiconductor wafers.

SILICON DIOXIDE (SiO₂)

The silicon/oxygen film most often used for dielectric applications; can be deposited via silane or TEOS; often called "oxide."

SILICON NITRIDE (Si₃N₄)

A silicon/nitrogen film dielectric deposited using plasma-enhanced or LPCVD.

SILICON-ON-INSULATOR (SOI)

A silicon wafer with a thin layer of oxide (SiO₂) buried in it. SOI substrates provide superior isolation between adjacent devices in an integrated circuit as compared to devices built into bulk wafers.

SPUTTERING

A method of depositing a film of material on a desired object.

STEPPER

Equipment used to transfer a reticle (mask) pattern onto a wafer.

STRAIN ENGINEERING

Processes used in semiconductor manufacturing that introduce stress into the underlying silicon structure by either compressing or expanding the silicon lattice structure, enabling electricity to move more easily through the transistor, increasing transistor performance.

SUBSTRATE

A wafer that is the basis for subsequent processing operations in the fabrication of semiconductor devices.

SUB-ATMOSPHERIC CHEMICAL VAPOR DEPOSITION (SACVD)

A term coined by Applied Materials to describe CVD processes performed slightly below atmospheric pressure using TEOS/ozone chemistry.

TETRAETHYLORTHOSILICATE (TEOS) (C₈H₂₀H₄Si)

A liquid source for oxide deposition.

THIN-FILM TRANSISTOR (TFT)

A metal-oxide-semiconductor field effect transistor manufactured with thin film technology. It typically uses thin films such as polycrystalline or amorphous silicon with a variety of insulating substrates. Used primarily in the manufacturing of active matrix LCDs.

THROUGHPUT

The number of wafers per hour through a machine, assuming 100% equipment uptime and a fully loaded machine.

TOPOGRAPHY

Refers to the layering of features on a device structure causing contours on the surface. The degree of flatness and/or smoothness is very important in wafer fabrication.

TRACK

A track-like set up which integrates several instruments needed to process photoresist (deposition, soft bake, exposure, developing, hard bake) in advanced semiconductor manufacturing.

TRANSISTOR

An electronic device that controls current flow and serves as the basic element of a computer chip. It consists of three terminals: a source, a gate, and a drain. Applying a voltage to the gate controls current flow between the source and the drain.

TRANSMISSION ELECTRON MICROSCOPE (TEM)

A transmission electron microscope that transmits a beam of electrons through an ultra-thin specimen. It operates on the same basic principle as the optical microscope by with much higher resolution.

TRENCH

A groove etched in a wafer to be used as part of a device structure.

TRENCH CAPACITOR

A capacitor built into an etched trench on the semiconductor substrate. The capacitance can be increased without increasing the area on the wafer needed to form the capacitor.

TUNGSTEN

A refractory metal used as an interconnect material.

ULTRA-SHALLOW JUNCTION (USJ)

An area of semiconductor manufacturing that is focused on reducing the junctions on the silicon substrate through ion implantation and rapid thermal processing.

ULTRAVIOLET (UV)

The invisible part of the light spectrum with wavelengths between 250 to 400 nanometers.

UNIFORM CAVITATION MEGASONICS™ (UCM)

A technology utilized to distribute energy evenly over the entire mask surface, avoiding the damage-causing spikes generated by traditional point-source megasonic cleans.

VIAS

Holes through dielectric layers, opened by etching. Metal will be deposited in the via to form a plug and create an interconnect between two metal lines.

WAFER

The thin, circular slice of pure silicon on which semiconductors are built.

WAFER AND MASK METROLOGY

An area of semiconductor manufacturing that is focused on ensuring the consistency and success of a microchip through automated systems.

WET CLEAN

A process for cleaning patterned wafers (using a liquid) between process steps.

YIELD

The percentage of wafers or die produced in a process that conforms to specifications.