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Endura® CIRRUS™ HT Co PVD

As integrated circuits and their components continue to scale downward, the dimensions of metal interconnects and contacts between components are also shrinking. One result is that the resistance in these connectors is increasing. To achieve more compact, faster electronic devices, resistance must be kept to a minimum so that further scaling is feasible.

The slowing effect produced by this higher resistance is often referred to as resistance-capacitance delay (or RC delay) and affects circuits in a variety of ways. Among its undesirable effects, RC delay can degrade the speed at which data are written to and read from DRAM structures via the bitline. In addition, higher resistance leads to higher power consumption, an undesirable side effect for mobile technologies.

Another byproduct of scaling is that aspect ratios are growing as feature density increases in advanced circuits. Consequently it is becoming more challenging to deposit films with the bottom coverage necessary for proper electrical performance of the final devices. Especially important in DRAM structures are the semiconductor-to-metal interfaces between the active region and the first level of metal interconnect. To achieve rapid and maximal charge transmission across these interfaces, a low-resistivity material (Co silicide) is used; its effectiveness relies on the deposition of a suitably thick and uniform interface layer.

The Endura Cirrus HT Co PVD system delivers the required silicide coverage through enhancements that overcome the challenges of shrinking contact area and growing aspect ratios. Using a high-frequency RF source to produce plasma containing a much higher concentration of metal ions than is possible with other source technologies, the system achieves excellent thickness and uniformity at the bottom of high aspect ratio features. A negative voltage on the wafer guides positive metal ions into narrow holes; because so many more metal ions are available, coverage at the bottom of high aspect ratio contact holes is two or three times as thick as that obtained with current technology. Consequently a robust layer of Co silicide is formed that lowers barriers to charge transmission between metal and semiconductor.

The system integrates Siconi pre-silicide clean with PVD Co and TiN cap deposition for the direct contact application in the DRAM periphery.

The Ohmic Contact Challenge

In a memory device, Ohmic contacts (semiconductor-to-metal interfaces) connect the active region and the metal wiring. As memory scaling continues, the area of the Ohmic contact shrinks approximately 70% node over node, while aspect ratios increase in the features within which the low-resistivity silicide must be deposited to form this contact. In 1xnm DRAM, these two factors are making it increasingly difficult to form a layer of Co silicide thick enough to ensure rapid, reliable transmission of an electrical charge from the active region through the contact to the upper levels of wiring, and back again.

The following animation illustrates the Ohmic contact concept and the beneficial effect that thick silicide coverage produced by the Endura Cirrus HT Co PVD system has on device performance.

RC delay is important because it can become a significant obstacle to continued downward scaling of logic and memory devices that drive the performance of today’s multi-functional, mobile consumer electronic devices. 

 

 

Active devices (transistors) in both logic and memory chips are electrically connected to each other and other areas of the chip with metal wiring. These wires are separated from each other using non-conducting (insulating) dielectric layers. In both logic and memory, the role of interconnects is to transmit signals from one area of the chip to another. The ability to do this as rapidly as possible, while minimizing signal losses in shrinking geometries, is critical for device scaling.

In logic, scaling implies area scaling, that is packing more and more circuits into a smaller area by means of materials and design innovations. In price-sensitive DRAM fabrication, costs must be aggressively controlled, so scaling focuses on obtaining progressively better performance from existing materials and design.

In general, the speed of signal propagation in logic and memory wires is governed by the same basic principles and depends on the product of resistance and capacitance (RC). Lowering both resistance and capacitance would be ideal. However, the costs of developing and integrating lower-capacitance insulating materials into the fabrication flow are especially high for memory manufacturers. Lowering resistance is therefore the preferred approach for scaling performance.

Different solutions are needed to address the RC challenge, depending on whether the charge travels vertically across different levels of wiring or laterally along the length of the conductor. In either case, though, the goal is to minimize the resistance of the metal wiring.

In the vertical dimension, solutions are aimed at minimizing interface resistance. Electrical contacts connect the active region of the device to the first level of metal wiring. A semiconductor-to-metal interface (or Ohmic contact) forms the junction between the active region and the metal contact. The objective is to ensure that an electrical charge can travel from the active region through the contact to the upper levels of wiring, and back again. To achieve rapid and maximal charge transmission across the Ohmic contact, a low-resistivity material is formed. Low-resistivity Co silicide has been adopted as the industry standard for this purpose; its effectiveness relies on the deposition of a uniform layer to form a robust Ohmic contact.

In the lateral dimension, solutions are aimed at optimizing the conductivity of the metal forming the wire. Line resistance, as it is called, is a function of both wire dimensions (width, height, length) and the specific properties of the material used to fabricate the wire–typically tungsten or copper.

The easiest means of lowering line resistance would be to increase the volume of the conducting metal, i.e., make the wires wider and taller. However, wider wires restrict scaling and taller wires increase capacitance and pose greater etch challenges. Consequently, lowering wire resistance in leading-edge devices focuses on improving the properties of the conducting material. See ENDURA® Versa™ XLR2 W PVD.