Endura® CIRRUS™ HT Co PVD
As integrated circuits and their components continue to scale downward, the dimensions of metal interconnects and contacts between components are also shrinking. One result is that the resistance in these connectors is increasing. To achieve more compact, faster electronic devices, resistance must be kept to a minimum so that further scaling is feasible.
The slowing effect produced by this higher resistance is often referred to as resistance-capacitance delay (or RC delay) and affects circuits in a variety of ways. Among its undesirable effects, RC delay can degrade the speed at which data are written to and read from DRAM structures via the bitline. In addition, higher resistance leads to higher power consumption, an undesirable side effect for mobile technologies.
Another byproduct of scaling is that aspect ratios are growing as feature density increases in advanced circuits. Consequently it is becoming more challenging to deposit films with the bottom coverage necessary for proper electrical performance of the final devices. Especially important in DRAM structures are the semiconductor-to-metal interfaces between the active region and the first level of metal interconnect. To achieve rapid and maximal charge transmission across these interfaces, a low-resistivity material (Co silicide) is used; its effectiveness relies on the deposition of a suitably thick and uniform interface layer.
The Endura Cirrus HT Co PVD system delivers the required silicide coverage through enhancements that overcome the challenges of shrinking contact area and growing aspect ratios. Using a high-frequency RF source to produce plasma containing a much higher concentration of metal ions than is possible with other source technologies, the system achieves excellent thickness and uniformity at the bottom of high aspect ratio features. A negative voltage on the wafer guides positive metal ions into narrow holes; because so many more metal ions are available, coverage at the bottom of high aspect ratio contact holes is two or three times as thick as that obtained with current technology. Consequently a robust layer of Co silicide is formed that lowers barriers to charge transmission between metal and semiconductor.
The system integrates Siconi pre-silicide clean with PVD Co and TiN cap deposition for the direct contact application in the DRAM periphery.
The Ohmic Contact Challenge
In a memory device, Ohmic contacts (semiconductor-to-metal interfaces) connect the active region and the metal wiring. As memory scaling continues, the area of the Ohmic contact shrinks approximately 70% node over node, while aspect ratios increase in the features within which the low-resistivity silicide must be deposited to form this contact. In 1xnm DRAM, these two factors are making it increasingly difficult to form a layer of Co silicide thick enough to ensure rapid, reliable transmission of an electrical charge from the active region through the contact to the upper levels of wiring, and back again.
The following animation illustrates the Ohmic contact concept and the beneficial effect that thick silicide coverage produced by the Endura Cirrus HT Co PVD system has on device performance.