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Using an STI gap-fill technology with a high-aspect-ratio process for 45-nm CMOS and beyond, Micro Magazine, June 2006†
Lithography Becomes Big Bottleneck, Electronic News, June 2006†
Strain Engineering in Non-Volatile Memories, Semiconductor International, April 2006†
A Reliable and Manufacturable Method to Induce a Stress of >1 GPa on a P-Channel MOSFET in High Volume Manufacturing, IEEE Electron Device Letters, Vol. 27, No. 2, February 2006 (263KB)
Porous low-k dielectrics using ultraviolet curing, Solid State Technology, September, 2005†
Production Processes for Inducing Strain in CMOS Channels, Semiconductor Fabtech, 26th Edition (322KB)
A Novel Sample Preparation Method of Four Point Bend Adhesion Test and Its Application on Cu and Low k Interfaces, Advanced Metallization Conference, 2004, pp 651-655 (152KB)
Development of Hermetic Oxide Films For Low-k Pore Sealing, Advanced Metallization Conference, 2004, pp 469-474 (161KB)
Plasma Enhanced CVD Low-k Black Diamond Film Formation Process For 65nm Technology Node, Advanced Metallization Conference, 2003, pp 543-547 (126KB)
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