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nanochip technology journal

Volume 12, Issue 2, 2014

To Our Readers

This issue of Nanochip features significant developments in widely divergent technologies, from interconnect to TSV and metrology to ion implantation. The first two in this list stand in stark contrast to each other from a dimensional perspective. Interconnect performance scaling is becoming increasingly challenging beyond the 20nm node. Without materials innovation, interconnect reliability and performance may be compromised from this point forward. Meanwhile, TSV dimensions are growing from the aspect ratio standpoint. At the start of this decade, aspect ratios were typically 5:1; now they can exceed 10:1. The depth of these vias can be 1000 times greater than conventional interconnect structures. Therefore, new advances in PVD technology are needed for TSV barrier/seed deposition.

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CVD Co-Based Metallization for <22nm Cu Interconnects

By Kavita Shah, Sree Kesapragada, Tae Hong Ha, and Jiang Lu

Aggressive interconnect scaling makes it highly challenging for incumbent PVD barrier and seed processes to achieve the coverage and adhesion required for void-free line and via fill at 22nm and below. Shrinking geometries also create higher current densities and greater propensity for electromigration (EM) failures. Ultra-thin CVD Co liners improve fill reliability and yield in small lines and vias, in combination with PVD barrier and seed technology. Depositing a post-planarization selective CVD Co cap enhances interface adhesion between the Cu lines and dielectric, reducing EM. Complete Cu encapsulation with CVD Co maximizes performance benefits for <22nm node fill and reliability.

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Extending PVD CuBS to Through-Silicon Vias

By Isaac Ow and Anthony Chan

Aspect ratios of through-silicon via (TSV) structures have increased to ≥10:1 in recent years. This development poses challenges for back-end‑of-line (BEOL) PVD processes that suffer line-of-sight limitations in achieving robust and void-free CuBS deposition. Refinements in PVD chamber design and parameter control are overcoming these issues, enabling chipmakers to extend existing infrastructure and knowhow to create high-reliability barriers and void-free gap fill in structures tens of microns deep.

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Enhancing Customized Dose Patterning for Higher Yields

By Stan Todorov, Greg Gibilaro, Norm Hussey, and John Sawyer

Deliberately non-uniform dose implants can improve device performance across the wafer by compensating for non-uniformities introduced by process steps other than implantation. In conjunction with improved controls on dose delivery and beam profile, new algorithms are enhancing the ability to customize dosing in up to seven zones for any scan line without rotating the wafer. These expanded capabilities offer chipmakers a versatile means of improving device performance and yield.

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Tilt-Beam CD-SEM for FinFET Metrology at the 1xnm Node

By Xiaoxiao Zhang and Alok Vaid, GLOBALFOUNDRIES, and
Jessica Hua Zhou, Adam Zhenhua Ge, and Ofer Adan

At the 1xnm node, 3D FinFETS pose a number of new metrology challenges. Gate and fin height are two of the most important process control parameters for which no inline in-die measurement has yet been implemented. In-column beam tilt CD-SEM for height measurement has been developed in response and is showing good results in the gate height application. Fin height measurement needs further refinement, yet initial results show promise that this method may become a viable metrology method for 3D devices.

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