Inspecting Solar Wafers: You Can't Fix What You Can't See
By Asaf Schlezinger
Innovative inspection and yield-management tools for solar manufacturers help boost yields and produce higher-quality products
In the semiconductor industry, statistical process control (SPC) techniques and yield-management systems are widely adopted tools. It’s hard to imagine running a fab without a closed-loop feedback system in place to closely monitor fab performance, tool variances, process windows, alerts and so on.
In the solar industry this is not yet the case. For example, crystalline silicon (c-Si) solar cell fabs may lack effective inspection techniques to identify incoming wafer defects that are strongly correlated to poor cell yields and quality.
Also, there may be no overall yield-management system (YMS) to effectively identify systemic issues and poorly performing tools that limit yield, which can be as low as 75%.
This is paradoxical because yields are critical to success in the solar industry, where margins are extremely tight given the lack of significant product differentiation and the extremely competitive markets for solar products. Applied Materials is addressing this issue by offering manufacturers of c-Si solar cells and c-Si wafers powerful technology to achieve higher yields.
The Applied Materials Vericell system is an inline photoluminescence-based wafer inspection technology that identifies important defects in incoming wafers and accurately predicts their likely impact on wafer breakage during subsequent processing. Standard manual or visual inspection techniques cannot find these defects, which include electrical dislocations and material impurities that impact efficiency.
Proprietary Applied Materials yield-management software also can be used with the Vericell system to collect and analyze real-time data to quickly identify and act on yield-impacting events throughout an entire wafer manufacturing line, thus boosting yields and enabling c-Si wafer manufacturers to certify that the wafers they supply are defect-free.
c-Si Wafer Defects and Breakage: A Strong Correlation
Inspection of bare c-Si wafers prior to processing them into solar cells is not yet a widely adopted practice. This is because there has been no clear standard on what to inspect or how to inspect, nor is there an accepted sampling strategy, and so the value of incoming wafer inspection has been unclear until now.
But studies enabled by Vericell inspection technology and conducted by Applied Materials in a Tier 1 solar cell manufacturing environment show definitively that (a) there is an overwhelming correlation between certain types of incoming wafer defects and subsequent wafer breakage during processing, and (b) when a cell breaks during processing, the breakage stems from defects in the wafer feedstock far more often than it does from mishandling by the cell processing tools.
For the study, a high volume of wafers was scanned on-the-fly with Applied’s Vericell technology to generate a sample group of wafers with defects. These wafers then were processed into cells, and the empirical breakage rate (BR) over a one-month period of production was compared with breakage predictions to determine their accuracy.
The predictions were based on the probability of breakage for each defect type and the likelihood of the defect appearing in the feedstock. Multiplying these two values and adding all defect types led to an overall prediction for breakage in the cell line.
First, empirical data was collected on the typical BR in the cell line. More than 2,000,000 wafers were inspected for key defects including edge chips, micro cracks, wafer thickness variation, saw marks and stains (see figure 1).
Figure 1. Some typical defects in c-Si solar wafers.
Figure 2. shows the empirical production data. Note that the BR is relatively stable, with a low standard deviation.
Next, the frequency of each defect type in the feedstock was examined over the same time period (see figure 3).
Figure 3. Defect frequency by type in c-Si solar cells (empirical results).
Then, the study addressed finding the probability of breakage per defect type during cell processing. To do that, ~250 wafers were selected from each defect type, totaling 2,500 wafers (250 wafers per type, 10 types), and were sent for cell processing. A control group of 250 random wafers was also taken.
The results were conclusive. While the empirical breakage rate during cell processing was around 2.35%, the BR of defective wafers was significantly higher. For example, micro-cracks in a wafer led to an 87% BR; V-shaped chips led to a BR of 81%; and deep saw marks led to a BR of 45%. Figure 4 summarizes these results.
The control group breakage rate, meanwhile, was 2.4%, similar to the empirical one-month data.
Figure 4. Test results from 2,500 wafers showing breakage rates for c-Si solar cells according to the type of defects in the wafers from which they were made. The control group was made up of 250 random wafers and gives an overall breakage rate for comparison.
Breakage probabilities for each defect type were calculated based on these results, as was the overall contribution by each defect type to cell line breakage. The overall result obtained, a breakage rate of 2.55%, is close to the empirical breakage rate of 2.35% that had been observed in the cell line. This strongly suggests that, in fact, defects in the incoming wafers are the dominant contributors to breakage in the cell line. Figure 5 provides the details of this calculation.
Figure 5. Predicted breakage rates for wafer defect types and their contributions to an overall predicted breakage rate for c-Si solar cells during processing. The net result of the calculations (a predicted breakage rate of 2.55%) is quite close to the breakage rate that was actually observed in the processing of 2MM wafers over a one-month period (2.35%).
Photoluminescence Drives Wafer Electrical Quality
Applied’s Vericell technology uses lasers to excite c-Si wafers, which causes them to emit light. A special camera is used to examine these emissions, the goal being to find areas of the wafer which emit only low levels of light, or none at all. These areas may be signs of dislocations within the wafer (e.g., recombination traps where the movement of charge-carrying electrons and holes is inhibited) or material impurities (see figure 6).
Figure 6. Examples of defects in c-Si wafers that negatively impact the electrical efficiency of solar cells made from those wafers. The defects were identified by the photoluminescence technology used in the Vericell inline inspection system from Applied Materials.
Special algorithms based on solar physics are used to analyze the defects to predict their impact on cell efficiency. Then, wafers that are predicted to perform poorly (below a specific efficiency level) can be scrapped rather than run through the costly process of cell manufacturing only to discover their low-efficiency performance.
Optimized Solar Manufacturing
The Vericell system uses Applied’s proprietary yield management system (YMS), which also enables wafer manufacturers to optimize their entire manufacturing line.
Solar c-Si wafer manufacturing starts with a polysilicon casting process in large furnaces, to produce silicon ingots that will later be cut into bricks. These bricks are sawed into wafers and then inspected for a variety of defects like thickness variation, saw marks, silicon defects, impurities and so on.
The Applied Materials YMS collects all history data on the wafers (serial number of furnace, serial number of saw tool, etc.) and, together with measured wafer parameters, can track back to identify poorly performing process tools, trends, drifts and other factors which impact yield.
One example taken from actual production line data illustrates how the system can help users find poorly performing saw machines. The example is from a fab in full production mode 24/7 at a capacity of ~70,000 wafers/day.
Whereas typical yields for saw machines are greater than 95%, one specific tool in this fab had a yield of less than 75% (see figure 7).
Figure 7. The Applied Materials yield-management system for c-Si wafers and cells identified a poorly performing saw machine.
Without a yield-management system in place, the fab likely would consider the issue to be a “normal” occurrence and continue the manufacturing process. However, the ability to highlight the tool’s poor performance enabled it to be taken down for preventive maintenance (PM) so the issue could be addressed. After PM, its yield increased 15%.
At a daily average capacity of ~5,000 wafers/hour and a wafer price of $0.85, the Applied Materials YMS therefore contributed $270K in additional revenue to this manufacturer.
Another example is shown in figure 8. This time the Applied Materials YMS identified furnaces that produced wafers with relatively high numbers of defects, directly leading to decreases in cell efficiency in all solar cells manufactured from those wafers. One of the furnaces was taken down for maintenance, and subsequently produced wafers with much higher (~0.25%) cell efficiencies.
Figure 8. The Applied Materials YMS identified specific furnaces that were producing relatively high numbers of wafers with defects.
Solar manufacturing is an intensely competitive business with low margins, and Applied Materials works hand-in-hand with solar manufacturers to provide solutions that will enable them to increase manufacturing efficiency and produce higher-quality products.
Offerings such as Vericell inspection technology, combined with effective yield-management, lead to increases in output of higher-quality, higher-efficiency c-Si wafers and cells, which can significantly improve profitability.
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