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Fan-Out is a Game Changer

David Lammers

In one sense, fan-out chip-scale packaging is just an evolutionary step, an advance on the fan-in CSP used in so many relatively low pin count chips. But look a bit deeper, and fan-out is perhaps the biggest thing to hit the semiconductor industry since immersion lithography and high-k dielectrics.

Jan Vardaman, president of packaging consultancy at TechSearch International (Austin, Texas) said fan-out packaging can be used for single or multiple die. “Fan-out can be a disruptive technology for several reasons. It can be used for multiple die, there is no substrate, and it can be done in a foundry.”

TSMC has been talking about its version of fan-out packaging, called integrated fan-out (InFO), for several years, and is one of a handful of companies already in production with fan-out packaging. In a financial results conference call with analysts in mid-October, TSMC co-CEO Mark Liu said TSMC’s InFO technology “will enter high-volume production with our 16-nanometer technology next year. We are currently working on the second-generation InFO technology for several projects of systems integration on 10 nanometer and 7 nanometer.”

Liu and co-CEO C.C. Wei fielded multiple questions on TSMC’s InFO technology, and said it can bring greater than 20% reduction in overall package thickness, a 20% speed gain, and 10% better power dissipation. TSMC has completed construction of the new facility in Longtan, near Hsinchu, Taiwan, for InFO volume production, with manufacturing equipment move-in “on schedule” and volume ramp-up scheduled for the second quarter of next year.

The TSMC executives did not mention Apple or its A10 application processor by name, but they said a large proportion of TSMC’s 16nm wafers will go through the fan-out packaging steps, with one customer accounting for much of it. According to Wei, “probably it will be adopted by the mobile processors first, and then applied to all other applications.”

First developed independently by Freescale and Infineon some 15 years ago, and subsequently licensed and developed by multiple OSATs, fan-out packaging is starting to see volume production. Vardaman said Intel, by virtue of its acquisition of Infineon’s wireless operation, is an early adopter. Intel’s Wireless Division uses fan-out packaging for an LTE multichip part that measures just 5.32 by 5.04 mm.

Some form of fan-out packaging has been used by Marvell and Maxim as well, Vardaman said. Amkor is bringing up a FO-WLP line in Korea, and ASE Group is building a fan-out line in Kaohsiung, Taiwan, with other major OSATs already in production or planning their versions of fan-out packaging. Cadence is among the EDA vendors who have released design tools that bridge the front-end and back-end design processes for packaging.

ASE senior fellow Bill Chen said ASE’s original motivation to license fan-out, and then later to work on its own implementation, was to increase the number of solder balls that could be placed under the increasingly tiny die. “The original fan-out motivation was to accommodate the die shrinks. Then, being creative engineers, we realized we can do a lot of other things with it, and create very thin packages,” he said.

Chen said the process involves dicing the chips on a silicon wafer, and then very precisely positioning them on a thin “reconstituted” or carrier wafer, which is then molded. The redistribution layer is created, and then solder balls are formed on top, just as in a wafer-level chip scale package. “The idea is very simple, to produce a reconstructed wafer and put it through the line,” he said, adding that “there are no laws of physics we are fighting, we are just fighting engineering, which means the challenges will be solved gradually. Fan-out is something that can be processed through wafer fab equipment—we need to pick the wafer up, place it, mold it, and bake it so the molding compound is cured. There is not any major wafer thinning needed like with TSVs. Clearly, fan-out technology is becoming more and more significant as we move further into the era of SIP and heterogeneous integration.”

Rozalia Beica, CTO at Yole Developpement, said TSMC has been telling its suppliers to be ready for volume fan-out processing beginning next year, perhaps in the 100,000 wafers-per-month range.

Beica estimated that an application processor can be combined with memories and other devices, with a 40% reduction in form factor compared with conventional flip chip packaging. And because fan-out does not require a substrate, the cost savings is substantial.

“There is a big difference in costs. Fan-out is lower cost than flip chip, which requires an organic substrate. And compared with silicon interposer, there is an even bigger cost difference, though maybe at this point there might be more performance with a silicon interposer,” she said.

How far fan-out packaging will go remains to be seen. But if multiple chips can be accommodated, it may cause some design teams to reconsider the need to create complex SoCs on advanced silicon, particularly for mobile and IoT systems. The analysts are predicting major shifts in how many chips will require more expensive types of packaging, such as flip chip, BGAs, interposers, and 3D integration.

“Everyone in the industry is scrambling to figure out the consequences” of fan-out packaging, Vardaman said, noting that “packaging is much more interesting than it used it be.”