Interconnect

Historically, metal interconnect wires consisted of aluminum. In today’s high-density ICs, wires are made of copper and form complex, multilevel networks. Copper has become the metal of choice for these advanced devices as it offers low resistivity (1.7 µohm/cm), which translates into faster integrated circuit speed. It also exhibits significantly less electromigration (10-100 times less than aluminum), which occurs when atoms drift off the interconnect line, potentially degrading performance by thinning a connection or by creating a short circuit.

A decade ago, the most advanced memory and logic devices consisted of 4 and 7 levels of interconnect, respectively. Dimensions were generous by today’s standards and wiring insulation was easily achieved with conventional silicate glass. Now, with growing numbers of transistors in modern microprocessors, 8-10 metal layers of interconnect are typical. This translates into more than 100km of copper wiring and ten billion vias per IC. Five years from now, at the 14 nm node, one can expect as many as 15 layers of interconnect and steep challenges in ensuring device speed, reliability, and endurance.

Overcoming these challenges requires more process sequence complexity in the interconnect, with new pre- and post-deposition treatments needed to achieve the required insulating film properties. Beyond the 14nm node, optical interconnects could emerge as the technology inflection that takes the industry to 20 Gbits/s and beyond.

As feature dimensions have shrunk, the widths of the metal lines and the spaces between those lines have shrunk as well. Silicate glass is no longer suitable as an insulating medium. Dielectrics with lower capacitance (or k value) are needed to enable faster device performance and lower power consumption. Over the past several device generations, Applied Materials has developed increasingly porous dielectric films as effective insulators with progressively lower k values. Reducing k value by 0.4—a film generation—reduces the interconnect power requirement by 10%. Applied’s dielectric films have become the industry standard used by fabs worldwide.

The performance of these low-k and ultra-low k films have been enhanced through ultraviolet curing and other post-treatments to optimize their mechanical strength and electrical properties. The films must withstand as many as 150 subsequent process steps, followed by chip packaging procedures. The harsh chemistries and plasmas involved can otherwise cause an undesirable increase in their k value. Innovative treatments developed by Applied strengthen the dielectrics, and electrical testing confirms their effectiveness in lowering the power consumption of the device.

Metallization processes have also encountered new challenges at smaller geometries. The seed layer is created by physical vapor deposition (PVD), a line-of-sight process in which copper is sputtered (or knocked) from a target and onto the wafer. In narrow, high-aspect-ratio features with perpendicular sidewalls, creating uniform seed coverage has become a major challenge, particularly towards the bottoms of the sidewalls. Discontinuities in this layer can lead to yield-limiting voids in the copper fill. At the same time, the higher aspect ratios also raised the risk of defective filling during the electrodeposition process. A long-established leader in PVD, Applied’s most recent innovation in this technology solves the seed layer coverage challenge through a bottom-up fill technique that eases the process requirements of downstream steps by partially filling the feature with copper, reducing the feature’s aspect ratio for electrodeposition. Complementing this advance in seed layer deposition, Applied’s electrodeposition technology delivers void-free copper plating and achieves uniform deposition across the wafer with optimized chemistries.

Chemical mechanical planarization (CMP) opportunity has grown as the number of interconnect levels has increased. Each deposited layer must be polished to ensure a flat surface for subsequent lithography. Without it, the layers would become increasingly uneven and extend outside the depth of focus of available lithography, interfering with the ability to pattern. Not only has copper CMP processing replaced aluminum CMP, but feature size and film thickness have shrunk dramatically. Applied’s innovations have heightened system sensitivity to topography and have integrated performance monitoring that enables exacting control of the planarization process.