After following Moore’s Law for nearly 40 years, increasing the storage capacity of traditional, two-dimensional memory chips by decreasing the size of its features, called “scaling,” is becoming very difficult.
For example, an advanced 25nm flash memory chip stores each bit of information using approximately 100 electrons. Containing those electrons reliably over millions of read/write cycles is a major challenge – and achievement.
To further increase storage density without scaling the size of the bits, manufacturers are turning to novel, more stacked architectures for both DRAM and NAND flash chips. Applied has developed the systems to enable this significant design change, providing manufacturers with the capability to produce high-reliability, low-cost memory chips for solid-state hard drives and other memory-intensive mobile applications.
Conventional DRAM designs surround each storage capacitor with its control circuitry and address lines. To pack more bits onto each chip, leading memory makers are instead burying the address lines underneath the capacitor in the silicon wafer. Applied has met this new design challenge with a full range of manufacturing systems targeted to enable this new approach.
Next-Generation NAND Chips
As further scaling of conventional flash memory cells becomes impractical, many leading manufacturers are developing a technology called "3D Stacked NAND." Multiple 2D memory arrays are fabricated on top of each other, thereby multiplying the capacity of the chip without reducing the size of each cell. Applied's innovative systems are helping flash memory manufacturers implement this exciting new technology.