Centura® RP Epi
CMOS technology requires two types of transistors: PMOS and NMOS. The former benefits best from applying compressive strain to the channel (squeezing the lattice), which decreases longitudinal spacing, enhances inter-atomic bond coupling, and facilitates hole mobility. For NMOS, tensile strain (stretching the lattice) is needed to increase longitudinal spacing and reduce the electron collisions that impede their mobility.
The Applied Centura RP Epi system has led the industry for over a decade, offering a range of epi solutions, from substrate formation to in-situ doping to selective SiGe for boosting PMOS transistor performance in advanced logic and memory devices. Applied’s proprietary epi technologies deliver excellent film properties, uniformity, and exceptionally low defect levels. Leveraging this expertise, new process capabilities now extend the Centura RP Epi system’s suite of applications to epi for NMOS transistors, enabling 20 percent gain in NMOS drive current (speed) for next-generation mobile technologies. This magnitude of performance improvement equates to scaling half a device node and effectively improves processing power to better support the ever advancing mobile applications.
Integrated on the Centura platform, Siconi technology delivers low-temperature, plasma-based, pre-clean capability without breaking vacuum, enabling true low-temperature epi for leading-edge technologies. Integrating these steps eliminates the HF dip and subsequent high-temperature hydrogen bake steps that pose growing challenges to devices beyond the 3x nm node. Further, it eliminates queue time and reduces interfacial contamination by more than an order of magnitude over stand-alone systems.