Centris® Sym3™ Etch
As semiconductor scaling has continued, increasingly rigorous requirements for precision and uniformity in chip fabrication have propelled the first comprehensive redesign of the silicon etch chamber in over a decade. The resulting Applied Centris Sym3 system delivers world-class cross-wafer uniformity with unprecedented within-chip feature control in critical etch applications for high-volume manufacturing at the 1x/10nm node and beyond.
At earlier technology nodes, when features were larger, a greater range in variation in etch depth, line or space width, or profile angle could be accommodated without affecting device performance. Similarly, occasional particles remaining on feature surfaces did not jeopardize device reliability. At the 1x/10nm node, however, the slightest differences in etch depth, line or space width, or profile angle can be fatal flaws in chip manufacture. And defect-free surfaces are equally essential.
To achieve the tight degree of within-chip etch control needed for such precise patterning, the new system creates a dramatically cleaner chamber environment that significantly accelerates the removal of etch byproducts—a major cause of variation. Both larger chamber volume and higher gas flows minimize the amount of byproduct that redeposits on the wafer, where it can pinch off narrow spaces and create etch depth variations, cause unacceptable variations between densely packed and isolated features, or exacerbate line edge roughness. Preventing byproduct accumulation also reduces particle formation and resultant defect creation.
narrow openings. Narrow features therefore cannot be etched
as deeply as wider ones, an effect known as depth loading.
features than on those of densely packed features. Consequently
their final widths differ, an effect known as pattern loading.